XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 158

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

DC and Switching Characteristics
Byte Peripheral Interface (BPI) Configuration Timing
Table 119: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
158
(Open-Drain)
T
T
T
T
T
Symbol
CCLK1
CCLKn
MINIT
INITM
INITADDR
RDWR_B
PROG_B
LDC[2:0]
HSWAP
CSO_B
A[23:0]
INIT_B
(Input)
(Input)
(Input)
(Input)
(Input)
CSI_B
M[2:0]
D[7:0]
CCLK
HDC
Figure 78: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration (BPI-DN mode shown)
Shaded values indicate specifications on attached parallel NOR Flash PROM.
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising
edge of INIT_B
Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising
edge of INIT_B
Minimum period of initial A[23:0] address cycle;
LDC[2:0] and HDC are asserted and valid
T
MINIT
<0:1:1>
HSWAP must be stable before INIT_B goes High and remain constant throughout configuration.
T
INITM
Pin initially pulled High by internal pull-up resistor if HSWAP input is Low.
Pin initially high-impedance (Hi-Z) if HSWAP input is High.
Description
0x00_0000
T
CCLK1
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Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
Byte 0
T
INITADDR
0x00_0001
(M[2:0]=<0:1:0>)
(M[2:0]=<0:1:1>)
BPI-DN:
BPI-UP:
Byte 1
T
AVQV
Data
Minimum
New ConfigRate active
T
CCLK1
Address
50
0
5
2
T
CCO
DS312-3 (v3.6) May 29, 2007
(see
(see
Data
T
T
DCC
CCLKn
Maximum
Product Specification
Table
Table
Address
5
2
-
-
Data
111)
111)
UG332_c5_08_110206
Address
T
T
cycles
Units
CCD
CCLK1
Data
ns
ns
R