XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 103

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Voltage Compatibility
The 2.5V V
the user I/Os are separately powered by their respective
VCCO_# supplies.
When connecting the Spartan-3E JTAG port to a 3.3V inter-
face, the JTAG input pins must be current-limited to 10 mA
or less using series resistors. Similarly, the TDO pin is a
CMOS output powered from +2.5V. The TDO output can
directly drive a 3.3V input but with reduced noise immunity.
See XAPP453: The 3.3V Configuration of Spartan-3 FPGAs
for additional information.
Table 66: Spartan-3E JTAG Device Identifiers
DS312-2 (v3.6) May 29, 2007
Product Specification
XC3S1200E
XC3S1600E
Spartan-3E
XC3S100E
XC3S250E
XC3S500E
TMS
TDO
TCK
TDI
FPGA
+2.5V
JTAG
CCAUX
R
JTAG
Mode
4-Bit Revision Code
supply powers the JTAG interface. All of
Step 0
P
‘1’
‘0’
‘1’
0x0
0x0
0x0
0x2
0x0
0x1
0x0
0x1
HSWAP
M2
M1
M0
TDI
PROG_B
TMS
TCK
Step 1
0x1
0x1
0x4
0x2
0x2
Spartan-3E
VCCINT
FPGA
+1.2V
GND
Figure 65: JTAG Configuration Mode
VCCAUX
Vendor/Device
VCCO_0
VCCO_2
0x1C 1A 093
0x1C 2E 093
0x1C 3A 093
0x1C 10 093
0x1C 22 093
DONE
Identifier
TDO
28-Bit
www.xilinx.com
VCCO_0
VCCO_2
+2.5V
JTAG Device ID
Each Spartan-3E FPGA array type has a 32-bit device-spe-
cific JTAG device identifier as shown in
28 bits represent the device vendor (Xilinx) and device iden-
tifer. The upper four bits, ignored by most tools, represent
the revision level of the silicon mounted on the printed cir-
cuit board.
specific stepping level.
JTAG User ID
The Spartan-3E JTAG interface also provides the option to
store a 32-bit User ID, loaded during configuration. The
User ID value is specified via the UserID configuration bit-
stream option, shown in
Using JTAG Interface to Communicate to a
Configured FPGA Design
After the FPGA is configured, using any of the available
modes, the JTAG interface offers a possible communica-
tions
BSCAN_SPARTAN3
JTAG instructions to create an internal boundary scan
chain.
JTAG
Mode
‘1’
‘0’
‘1’
P
channel
Table 66
HSWAP
M2
M1
M0
TDI
TMS
TCK
PROG_B
to
Spartan-3E
VCCINT
design primitive provides two private
associates the revision code with a
+1.2V
GND
FPGA
Table 68, page
internal
VCCAUX
VCCO_0
VCCO_2
DONE
TDO
Functional Description
FPGA
Table
110.
VCCO_0
VCCO_2
+2.5V
66. The lower
DS312-2_56_021405
logic.
TMS
TCK
The
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