XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 117

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

DS312-2 (v3.6) May 29, 2007
Product Specification
03/16/07
05/29/07
11/09/06
Date
R
Version
3.5
3.6
3.4
Updated the description of the
is no longer supported. Updated
Replaced missing text in
Updated parallel NOR Flash devices in
was added beginning with ISE 8.1i iMPACT software for STMicro and Atmel SPI PROMs. Updated
Table 70
Module 2 to Production status.
Added information about new Spartan-3 Generation user guides
Generation Design Documentation
Spartan-3 Generation FPGA User Guide and to UG332: Spartan-3 Generation
Configuration User Guide. Added note about possible JTAG configuration issues when the
FPGA mode pins are set for Master mode and using software prior to ISE 9.1.01i
Mode). Removed a few lingering references to “weak” pull-up resistors, including in
Figure
Slave Parallel Mode
Added information about HSWAP and PCI differences between steppings to
Removed “Performance Differences between Global Buffers” to match improved specs in
Module 3. Updated PROG_B pulse width descriptions to match specification in Module 3.
12. Removed vestigial references regarding the LDC[2:0] and HDC pins during
and
Table 71
as Stepping 1 is in full production. Freshened various hyperlinks. Promoted
configuration. These pins are not used in this configuration mode.
www.xilinx.com
Clock
Input Delay
Buffers/Multiplexers. Updated SPI Flash devices in
Figure
Table
5. Updated
Available). Added cross-references to UG331:
Functions. The
Revision
60. Direct, SPI Flash in-system
Table 6
for improved PCI input voltage tolerance.
ODDR2
flip-flop with C0 or C1 Alignment
(New Spartan-3
Functional Description
Programming Support
Table
Table
(JTAG
52.
70.
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