XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 74

no-image

XC3S100E

Manufacturer Part Number
XC3S100E
Description
Spartan-3e Fpga Family Complete Data Sheet
Manufacturer
Xilinx Corp.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC3S100E
Manufacturer:
XILINX
0
Part Number:
XC3S100E-4CP132C
Manufacturer:
XILINX
0
Part Number:
XC3S100E-4CP132I
Manufacturer:
XILINX
0
Part Number:
XC3S100E-4CPG132C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S100E-4CPG132C
Manufacturer:
XILINX
0
Part Number:
XC3S100E-4CPG132C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Part Number:
XC3S100E-4CPG132C
0
Part Number:
XC3S100E-4TQ144C
Manufacturer:
XILINX
Quantity:
57
Part Number:
XC3S100E-4TQ144I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Part Number:
XC3S100E-4TQG144C
Manufacturer:
XILINX
Quantity:
308
Functional Description
Table 49: Serial Master Mode Connections
74
HSWAP
M[2:0]
DIN
CCLK
DOUT
INIT_B
Pin Name
P
FPGA Direction
bidirectional I/O
Open-drain
Output
Output
Input
Input
Input
User I/O Pull-Up Control. When Low
during configuration, enables pull-up
resistors in all I/O pins to respective I/O
bank V
0: Pull-ups during configuration
1: No pull-ups
Mode Select. Selects the FPGA
configuration mode. See
Considerations for the HSWAP, M[2:0],
and VS[2:0]
Serial Data Input.
Configuration Clock. Generated by
FPGA internal oscillator. Frequency
controlled by ConfigRate bitstream
generator option. If CCLK PCB trace is
long or has multiple connections,
terminate this output to maintain signal
integrity. See
Considerations.
Serial Data Output.
Initialization Indicator. Active Low. Goes
Low at start of configuration during
Initialization memory clearing process.
Released at end of memory clearing,
when mode select pins are sampled.
Requires external 4.7 kΩ pull-up resistor
to VCCO_2.
CCO
input.
Pins.
CCLK Design
Description
www.xilinx.com
Design
Drive at valid logic level
throughout configuration.
M2 = 0, M1 = 0, M0 = 0.
Sampled when INIT_B goes
High.
Receives serial data from
PROM’s D0 output.
Drives PROM’s CLK clock
input.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration, this
pin connects to DIN input of
the next FPGA in the chain.
Connects to PROM’s
OE/RESET input. FPGA
clears PROM’s address
counter at start of
configuration, enables
outputs during configuration.
PROM also holds FPGA in
Initialization state until PROM
reaches Power-On Reset
(POR) state. If CRC error
detected during configuration,
FPGA drives INIT_B Low.
During Configuration
DS312-2 (v3.6) May 29, 2007
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O. If unused in
the application, drive
INIT_B High.
Product Specification
After Configuration
R

Related parts for XC3S100E