XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 134

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

DC and Switching Characteristics
Table 92: Timing for the IOB Three-State Path
134
Notes:
1.
2.
Synchronous Output Enable/Disable Times
T
T
Asynchronous Output Enable/Disable Times
T
Set/Reset Times
T
T
IOCKHZ
IOCKON
GTS
IOSRHZ
IOSRON
Symbol
The numbers in this table are tested using the methodology presented in
Table 76
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from
(2)
(2)
and
Table
Time from the active transition at
the OTCLK input of the
Three-state Flip-Flop (TFF) to
when the Output pin enters the
high-impedance state
Time from the active transition at
TFF’s OTCLK input to when the
Output pin drives valid data
Time from asserting the Global
Three State (GTS) input on the
STARTUP_SPARTAN3E
primitive to when the Output pin
enters the high-impedance state
Time from asserting TFF’s SR
input to when the Output pin
enters a high-impedance state
Time from asserting TFF’s SR
input at TFF to when the Output
pin drives valid data
79.
Description
LVCMOS25,
12 mA output
drive, Fast slew
rate
LVCMOS25,
12 mA output
drive, Fast slew
rate
LVCMOS25,
12 mA output
drive, Fast slew
rate
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Conditions
Table 94
Table
93.
Device
and are based on the operating conditions set forth in
All
All
All
All
All
Abs. Max.
0.60
1.09
3.43
0.85
1.34
-0
Speed Grade
DS312-3 (v3.6) May 29, 2007
Max
1.49
2.70
8.52
2.11
3.32
-5
Product Specification
Max
1.71
3.10
9.79
2.43
3.82
-4
Units
ns
ns
ns
ns
ns
R