XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 153

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Master Serial and Slave Serial Mode Timing
Table 115: Timing for the Master Serial and Slave Serial Configuration Modes
DS312-3 (v3.6) May 29, 2007
Product Specification
(Input/Output)
Notes:
1.
2.
(Open-Drain)
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
F
Symbol
CCO
DCC
CCD
CCH
CCL
CCSER
PROG_B
The numbers in this table are based on the operating conditions set forth in
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
(Output)
INIT_B
(Input)
(Input)
DOUT
CCLK
DIN
R
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
The time from the setup of data at the DIN pin to the active edge of
the CCLK pin
The time from the active edge of the CCLK pin to the point when
data is last held at the DIN pin
High pulse width at the CCLK input pin
Low pulse width at the CCLK input pin
Frequency of the clock signal at
the CCLK input pin
Figure 75: Waveforms for Master Serial and Slave Serial Configuration
Description
T
DCC
Bit 0
No bitstream compression
With bitstream compression
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T
CCD
Bit 1
Table
76.
T
T
Master
Master
Master
Slave/
Slave
Slave
Slave
MCCL
SCCL
Both
Both
Both
DC and Switching Characteristics
Bit n
1/F
CCSER
T
CCO
Bit n-64
All Speed Grades
Bit n+1
11.0
Min
1.5
T
T
0
0
0
MCCH
SCCH
See
See
See
See
Bit n-63
Table 113
Table 114
Table 113
Table 114
66
Max
10.0
20
-
-
(2)
DS312-3_05_103105
Units
MHz
MHz
ns
ns
ns
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