XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 161

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Revision History
The following table shows the revision history for this document.
DS312-3 (v3.6) May 29, 2007
Product Specification
03/01/05
11/23/05
03/22/06
04/07/06
05/19/06
05/30/06
11/09/06
03/16/07
05/29/07
Date
R
Version
3.2.1
1.0
2.0
3.0
3.1
3.2
3.4
3.5
3.6
Initial Xilinx release.
Added AC timing information and additional DC specifications.
Upgraded data sheet status to Preliminary. Finalized production timing parameters. All
speed grades for all Spartan-3E FPGAs are now Production status using the v1.21 speed
files, as shown in
and clock-to-output timing based on final characterization, shown in
system-synchronous input setup and hold times based on final characterization, shown in
Table 86
adjustments for LVPECL_25, DIFF_SSTL and DIFF_HSTL I/O standards that supersede
the v1.21 speed file values, in
set/reset delays in
Increased T
in
clock buffer limits in
parameters for remainder of Step 0 device; added improved Step 1 DCM performance to
Table
specification, T
(T
Table
Table
Improved SSO limits for LVDS_25, MINI_LVDS_25, and RSDS_25 I/O standards in the QFP
packages
Clarified that 100 mV of hysteresis applies to LVCMOS33 and LVCMOS25 I/O standards
(Note 4,
Corrected various typos and incorrect links.
Improved absolute maximum voltage specifications in
overshoot allowance. Widened the recommended voltage range for PCI and PCI-X
standards in
v1.26 speed file. Added
time all devices became Production status. Added absolute minimum values for
Table
IFD_DELAY_VALUE settings in
source-synchronous input capture sample window. Promoted Module 3 to Production
status. Synchronized all modules to v3.4.
Based on extensive 90 nm production data, improved (reduced) the maximum quiescent
current limits for the I
of 50%.
Added note to
t
200 MHz for Stepping 1 in
RPW_CLB
SMCCD
Table 98
103,
103,
119. Added MultiBoot timing specifications to
91, and
Table
) in
and
in
(Table
Table
Table
and SRL16 timing in
AS
Table
Table 97
Table
Table
Table
79). Other minor edits.
Table 73
slice flip-flop timing by 100 ps in
INIT
96). Removed potentially confusing Note 2 from
104,
104,
Table
, in
116. Improved the DCM performance for the XC3S1200E, Stepping 0 in
79. Clarified Note 2,
Table
87. Updated other I/O timing in
Table
92. Updated pin-to-pin setup and hold timing based on default
CCINTQ
Table
to match value in speed file. Improved CLKOUT_FREQ_CLK90 to
Table
Table
www.xilinx.com
Table 84
83. Expanded description in Note 2,
and
92. Added XC3S100E FPGA in CP132 package to
100. Updated block RAM timing in
Table
110. Increased data hold time for Slave Parallel mode to 1.0 ns
, I
105, and
105, and
Table 74
CCAUXQ
Table 90
Table
Table
to summarize the history of speed file releases after which
104.
, and I
regarding HSWAP in step 0 devices. Updated
Table
Table
86,
99. Updated global clock timing, removed left/right
Table
and
Revision
Table
106. Added minimum INIT_B pulse width
106. Corrected links in
CCOQ
Table
82. Improved various timing specifications for
Table
87, and
specifications in
93. Reduced I/O three-state and
Table
Table
97. Updated distributed RAM timing
Table
DC and Switching Characteristics
Table
89. Provided input and output
121.
72, providing additional
Table
Table
89. Added
Table
Table 78
77. Updated pin-to-pin
Table 117
102. Added DCM
Table
77.
Table 88
85. Updated
by an average
Table
and
Table
95.
about
85,
161