TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 99

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

3.7.2
System Clock
xxx: Don’t care
<SYSCK>
Selection
SYSCR1
1 (fs)
0 (fc)
Operation of Each Circuit
(1) Prescaler
(2) Up counters (UC0 and UC1)
the prescaler clock selection register SYSCR0<PRCK1:0>.
timer control register. Setting <TA0PRUN> to 1 starts the count; setting <TA0PRUN>
to 0 clears the prescaler to “0” and stops operation. Table 3.7.2 shows the various
pre-scaler output clock resolutions.
specified by TA01MOD.
the TA0IN pin or one of the three internal clocks φT1, φT4 or φT16. The clock setting is
specified by the value set in TA01MOD<TA01CLK1:0>.
overflow output from UC0 is used as the input clock. In any mode other than 16-bit
timer mode, the input clock is selectable and can either be one of the internal clocks
φT1, φT16 or φT256, or the comparator output (The match detection signal) from
TMRA0.
TA01RUN<TA0RUN> and TA01RUN<TA1RUN> can be used to stop and clear the
up-counters and to control their count. A reset clears both up counters, stopping the
timers.
Prescaler Clock
A 9-bit prescaler generates the input clock to TMRA01.
The “φT0” as the input clock to pre-scaler is a clock divided by 4 which selected using
The prescaler’s operation can be controlled using TA01RUN<TA01PRUN> in the
These are 8-bit binary counters which count up the input clock pulses for the clock
The input clock for UC0 is selectable and can be either the external clock input via
The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the
For
<PRCK1:0>
(fc/16 clock)
Selection
SYSCR0
(f
FPH
00
10
each
)
Table 3.7.2 Prescaler Output Clock Resolution
interval
<GEAR2:0>
XXX
000 (fc)
001 (fc/2)
010 (fc/4)
011 (fc/8)
100 (fc/16)
XXX
Gear Value
SYSCR1
timer
91C016-97
2
2
2
2
2
2
2
3
3
4
5
6
7
7
/fs (244
/fc (0.3
/fc (0.6
/fc (1.2
/fc (2.4
/fc (4.7
/fc (4.7
the
φ T1
µ
µ
µ
µ
µ
µ
µ
s)
s)
s)
s)
s)
s)
s)
timer
Prescaler Output Clock Resolution
2
2
2
2
2
2
2
5
5
6
7
8
9
9
/fs (977
/fc (1.2
/fc (2.4
/fc (4.7
/fc (9.5
/fc (19.0
/fc (19.0
φ T4
operation
µ
µ
µ
µ
µ
s)
s)
s)
s)
µ
µ
s)
s) 2
s) 2
2
2
2
2
2
at fc = 27 MHz, fs = 32.768 kHz
7
7
8
9
10
11
11
/fs (3.9
/fc (4.7
/fc (9.5
/fc (19.0
/fc (37.9
/fc (75.9
/fc (75.9
φ T16
control
µ
µ
µ
s)
s)
s)
µ
µ
µ
µ
s) 2
s) 2
s) 2
s) 2
2
2
2
11
11
12
13
14
15
15
/fs (62.5
/fc (75.85
/fc (151.7
/fc (303.4
/fc ( 606.8
/fc (1214
/fc (1214
register
φ T256
TMP91C016
2008-02-20
µ
µ
µ
s)
µ
µ
µ
µ
s)
s)
s)
s)
s)
s)
bits