TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 45

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

D0 to D15
WR
A0 to A23
/
HWR
RD
X1
Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows.
States 1 to 3: Instruction fetch cycle (Gets next address code).
States 4 to 5: Micro DMA read cycle
State 6: Dummy cycle (The address bus remains unchanged from state 5)
States 7 to 8: Micro DMA write cycle
Note 1: If the source address area is an 8-bit bus, it is increased by two states.
Note 2: If the destination address area is an 8-bit bus, it is increased by two states.
1 state
DM1
In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking
“Interrupt specified by micro DMA start vector” (in the Table 3.4.1 ) and reading interrupt vector with
setting below. The vector shifts to that of INTyyy at the time.
This is because the priority level of INTyyy is higher than that of INTxxx.
In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished.
And INTyyy is generated regardless of transfer counter of micro DMA.
INTxxx: level 1 without micro DMA
INTyyy: level 6 with micro DMA
transfer, and 4-byte transfer. After a transfer in any mode, the transfer
source/destination addresses are increased, decreased, or remain unchanged.
from I/O to I/O. For details of the transfer modes, see 3.4.2 (4) “Detailed description of
the transfer mode register”. As the transfer counter is a 16-bit counter, micro DMA
processing can be set for up to 65536 times per interrupt source. (The micro DMA
processing count is maximized when the transfer counter initial value is set to 0000H.)
start vectors of Table 3.4.1 and by the micro DMA soft start, making a total of 35
interrupts.
address INC mode (Except for counter mode, the same as for other modes).
source/transfer destination addresses both even-numberd values).
Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (One-word)
This simplifies the transfer of data from I/O to memory, from memory to I/O , and
Micro DMA processing can be started by the 34 interrupts shown in the micro DMA
Figure 3.4.2 shows the word transfer micro DMA cycle in transfer destination
(The conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer
If the source address area is a 16-bit bus and the address starts from an odd number, it
is increased by two states.
If the destination address area is a 16-bit bus and the address starts from an odd
number, it is increased by two states.
DM2
If 3 bytes and more instruction codes are inserted in the instruction queue buffer,
this cycle becomes a dummy cycle.
DM3
Figure 3.4.2 Timing for Micro DMA Cycle
DM4
Transfer source address
(Note 1)
DM5
Input
91C016-43
DM6
DM7
Transfer destination
(Note 2)
address
Output
DM8
TMP91C016
2008-02-20