TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 16

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TMP91xy16FG

Manufacturer Part Number
TMP91xy16FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy16FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
-
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
31
Power Supply Voltage(v)
2.7 to 3.6
Note 1: It’s prohiibited to control DFM in SLOW mode when shifting from SLOW mode to NORMAL mode with use of DFM.
Note 2: If you shift from NORMAL mode with use of DFM to NORMAL mode, the above two instructions should be separated
Note 3: It’s prohibited to shift from NORMAL mode with use of DFM to STOP mode directly. You should set NORMAL mode
The clock frequency input from the X1 and X2 pins is called fc, and the clock frequency input from the
XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1<SYSCK> is called the system
clock f
to as one state.
(Operate oscillator and DFM)
clock mode (X1, X2, XT1 and XT2 pins) and (c) Triple clock mode (the X1, X2, XT1 and XT2 pins
and DFM).
FPH
(DFM Start up/Stop/Change Write to DFMCR0<ACT1:0> register)
into two procedures as below. Change CPU clock → Stop DFM circuit.
once, and then shift to STOP mode. (You should stop high frequency oscillator after you stop DFM.)
(Operate only oscillator)
(Operate only oscillator)
(Operate only oscillator)
(Operate only oscillator)
(I/O operate)
The clock operating modes are as follows: (a) Single clock mode (X1, X2 pins only), (b) Dual
Figure 3.3.1 shows the system clock block diagrams.
IDLE2 mode
IDLE1 mode
. The system clock f
(I/O operate)
IDLE1 mode
(I/O operate)
(I/O operate)
(I/O operate)
IDLE2 mode
IDLE2 mode
IDLE1 mode
IDLE2 mode
IDLE1 mode
IDLE2 mode
IDLE1 mode
Interrupt
Instruction
Instruction
Figure 3.3.1 System Clock Block Diagram
SYS
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
(4 × f OSCH /gear
* Note
is defined as the divided clock of f
NORMAL mode
Using DMF
(b)
(c)
(a)
value/2)
Instruction
Dual clock mode transition figure
Triple clock mode trasition figure
Single clock mode transition figure
91C016-14
(f
(f
(f
(Stops all circuits)
OSCH
OSCH
OSCH
NORMAL
NORMAL
NORMAL mode
SLOW mode
STOP mode
(f
(f
OSCH
(f
OSCH
Instruction
Reset
Reset
/gear value/2)
OSCH
/gear value/2)
/gear value/2)
(fs/2)
Instruction
* Note
Reset
Release reset
Release reset
Release reset
/32)
mode
/32)
mode
/32)
Interrupt
SLOW mode
Instruction
Interrupt
(fs/2)
Instruction
FPH
Instruction
Instruction
, and one cycle of f
Interrupt
Instruction
Instruction
Interrupt
(Stops all circuits)
(Stops all circuits)
(Operate only oscillator)
STOP mode
STOP mode
SYS
TMP91C016
IDLE2 mode
(I/O operate)
IDLE1 mode
2008-02-20
is regret

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