TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 91

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

Read-
modify-
write
instructions
are
prohibited.
Read-
modify-
write
instructions
are
prohibited.
Read
modify-
write
instructions
are
prohibited.
Read-
modify-
write
instructions
are
prohibited.
Read-
modify-
write
instructions
are
prohibited.
B0CS
(00C0H)
B1CS
(00C1H)
B2CS
(00C2H)
B3CS
(00C3H)
BEXCS
(00C7H)
0
1
0
1
Master enable bit
CS2 area selection
Bit symbol
Read/Write
After reset
Function
Bit Symbol
Read/Write
After reset
Function
Bit Symbol
Read/Write
After reset
Function
Bit Symbol
Read/Write
After reset
Function
Bit Symbol
Read/Write
After reset
Function
Disable
Enable
16-Mbyte area
Specified address area
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
B0E
B1E
B2E
B3E
W
W
W
7
0
0
1
0
Figure 3.6.5 Chip Select/Wait Control Registers
CS2 area
selection
0: 16-Mbyte
1: CS area
area
B2M
6
0
Chip Select/Wait Control Register
Chip select output waveform
selection
For DRAM only CS3
setting
00 For ROM/SRAM
01 Don’t care
10 Don’t care
11 Don’t care
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
11:
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
11:
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
11:
Chip select output
waveform selection
00: For ROM/SRAM
01: Don’t care
10: For DRAMC
11: Don’t care
B0OM1
B1OM1
B2OM1
B3OM1
5
0
0
0
0
Don’t care
Don’t care
Don’t care
91C016-89
B0OM0
B1OM0
B2OM0
B3OM0
4
0
0
0
0
W
Data bus
width
0: 16 bits
1: 8 bits
Data bus
width
0: 16 bits
1: 8 bits
Data bus
width
0: 16 bits
1: 8 bits
Data bus
width
0: 16 bits
1: 8 bits
Data bus
width
0: 16 bits
1: 8 bits
BEXBUS
B0BUS
B1BUS
B2BUS
B3BUS
3
0
0
0
0
0
W
W
W
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits 110: 4 waits
011: 0 waits
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits 110: 4 waits
011: 0 waits
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits 110: 4 waits
011: 0 waits
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits 110: 4 waits
011: 0 waits
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits 110: 4 waits
011: 0 waits
BEXW2
B0W2
B1W2
B2W2
B3W2
0
1
Data bus width selection
Number of address area waits
2
0
0
0
0
0
(See 3.6.2 (3) Wait control.)
16-bit data bus
8-bit data bus
0
BEXW1
B0W1
B1W1
B2W1
B3W1
100: Reserved
101: 3 waits
111: 8 waits
100: Reserved
101: 3 waits
111: 8 waits
100: Reserved
101: 3 waits
111: 8 waits
100: Reserved
101: 3 waits
111: 8 waits
100: Reserved
101: 3 waits
111: 8 waits
1
0
0
0
0
0
BEXW0
B0W0
B1W0
B2W0
B3W0
0
0
0
0
0
0
TMP91C016
2008-02-20