TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 225

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

(4) The voltage level comparison and comparison result interrupt
(5) VLD comparison time
(6) Housing and readout of VLD comparison result
INTVLD0, INTVLD1 and INTVLD2 can mask own interrupt at source level, but at
interrupt circuit, these interruptions are recognized as non-maskable interruption.
Because it is the non-maskable interruption entirely, interrupt level is fixed in 7.
Besides, as non-maskable interruption, there are NMI terminal and watchdog timer.
And I accept interrupt according to default priority when interrupt request of same
level occurred simultaneously. Please refer to the control of interrupt controller in
detail.
It is stored away successively from the moment that established 1 in <INT*EN> to
<VLD*IN> after movement started it by establishing 1 in <V*EN> of VLD mode
control register.
When the voltage falls than setting detect value the input voltage from VLD* terminal
this flag, 1 is led, and 0 is led when higher than setting detect value.
comparison movement at any time, and data will change, but the contents which data
changed into last when comparison movement was stopped are maintained. On this
account I can clear these data. In other words a write of 0 data becomes possible
(Impossible a write of 1 data).
edge interrupt request with a signal after it was controlled with a gate for interrupt
permission flag.
order.
Next 3 are prepared in interrupt generated by comparison result of three VLD.
Comparison state per 1 channel is 8064 states (1 ms at f
VLD voltage comparison result is stored in <VLD*IN>: bit4 of VLDCR0 to VLDCR2.
VLD comparison result housing flag <VLD*IN> shows VLD comparison result.
And this comparison result leads the output result of VLD. It is updated during data
This signal comes to demand interrupt for CPU and, as for the interrupt, it is done
I ask for the voltage setting, movement, interrupt to establish it by the following
Note: * shows 0, 1 and 2 (3 channels)
When setting detect voltage .....
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Mask to interruption
Disable VLD operation
Change value
Enable VLD operation
Need set up time (More 1 ms)
Clear write <VLD*IN>
Release interruption mask
91C016-223
FPH
= 16 MHz).
TMP91C016
2008-02-20