TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 19

no-image

TMP91xy16FG

Manufacturer Part Number
TMP91xy16FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy16FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
-
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
31
Power Supply Voltage(v)
2.7 to 3.6
DFMCR0
DFMCR1
Symbol
DFM
Control
Register 0
DFM
Control
Register 1
Name
1.
2.
3.
Please refer to 3.3.5 “Clock Doubler (DFM)” for the details.
Limitation point on the use of DFM
It’s prohibited to execute DFM enable/disable control in the SLOW mode (fs) (write to
DFMCR0<ACT1:0> = “10”). You should control DFM in the NORMAL mode.
If you stop DFM operation during using DFM (DFMCR0<ACT1:0> = “10”), you
shouldn't executions should be separated into two procedures as showing below.
If you stop high-frequency oscillator during using DFM (DFMCR0<ACT1:0> = “10”),
you should stop DFM before you stop high-frequency oscillator.
Address
E8H
E9H
LD
LD
00
01
10
11
ACT1
STOP
R/W
R/W
RUN
RUN
RUN
DFM
(DFMCR0), C0H
(DFMCR0), 00H
D7
7
0
0
STOP
STOP
STOP
RUN
LUP Select f FPH
Figure 3.3.4 SFR for DFM
ACT0
R/W
f
f
f
f
R/W
OSCH
OSCH
DFM
OSCH
D6
6
0
0
Input frequency 4 to 6.75 MHz (at 2.7 V to 3.6 V): Write 0BH
Input frequency 2 to 2.5 MHz (at 2.0 ± 10%): Write 1BH
91C016-17
Lockup
status flag
0: End
1: Not end
DLUPFG
R/W
D5
R
5
0
0
; Change the clock f
; DFM stop
Lockup time
0: 2
1: 2
DLUPTM
12
10
R/W
R/W
/f OSCH
/f OSCH
D4
4
0
1
DFM revision
DFM
R/W
D3
3
0
to f
OSCH
R/W
D2
2
0
R/W
D1
1
1
TMP91C016
2008-02-20
R/W
D0
0
1

Related parts for TMP91xy16FG