TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 65

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

P6
(0012H)
P6CR
(0014H)
P6FC
(0015H)
P6FC2
(001BH)
P6UE
(0018H)
P6FC3
(0010H)
Note 1: Read-modify-write is prohibited for registers P6CR, P6FC, P6FC2, P6FC3 and P6UE.
Note 2: When P63 pin is used as a
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
0: Port
1:
0: <P67F>
1:
Pull-up
resistor
0: Disable
1: Enable
REFOUV
P67F2
LCAS
LDS
P67C
P67U
P67F
P67
7
7
7
7
7
7
or
0
0: Port
1:
0: <P66F>
1:
Pull-up
resistor
0: Disable
1: Enable
P66F2
UCAS
or
UDS
P66C
P66U
P66F
P66
6
6
6
6
6
6
0: Input
WE
CS3
Data from external port (Output latch register is set to 1)
Figure 3.5.8 Port 6 Register
0: Port
1: EA25
0: <P65F>
1:
Pull-up
resistor
0: Disable
1: Enable
LCLK2
selection
0: Normal
1: LCLK2
pin and
P65F2
P65F3
CS2C
P65C
P65U
P65F
Port 6 Function Register2
Port 6 Function Register3
P65
Port 6 Function Register
W
W
W
Port 6 Control Register
5
5
0
5
5
5
5
0
Port 6 UE Register
91C016-63
Port 6 Register
RAS
1: Output
W
0
1
0: Port
1: EA24
0: <P64F>
1:
Pull-up
resistor
0: Disable
1: Enable
, set chip select/wait control register B3CS<B3OM1:0> to 10.
P64F2
CS2B
P64C
P64U
P64F
P64
4
4
4
4
4
4
R/W
W
0
0: Port
1:
Always
write “0”
Pull-up
resistor
0: Disable
1: Enable
CS3
P63C
P63U
P63F
P63
3
3
3
3
–
3
0
3
0:
1:
0:
1:
P65F2D
CS2
CS2A
<P65F2>
VEECLK
P62F
2
2
2
2
2
2
0: Port
1:
Always
write “0”
Pull-up
resistor
0: Disable
1: Enable
CS1
P61C
0: Input 1: Output
P61F
P61U
P61
W
1
1
1
1
1
1
–
0
W
0
1
Pull-up
resistor
0: Disable
1: Enable
LCLK0
selection
0: Normal
1: LCLK0
0: Port
1:
P60F3
P60C
CS0
P60F
P60U
P60
TMP91C016
W
0
0
0
0
0
0
0
2008-02-20