TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 36

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

<RSYSCK>
SYSCR0
0 (fc)
1 (fs)
Interrupt for
Figure 3.3.8 Timing Chart for STOP Mode Halt State Cleared by Interrupt
D0 to D15
A0 to A23
Table 3.3.6 Sample Warm-up Times after Clearance of STOP Mode
release
c. STOP mode
WR
RD
oscillator pin status in STOP mode depends on the settings in the
SYSCR2<DRVE> register. Table 3.3.7, Table 3.3.8 summarizes the state of these
pins in STOP mode.
warm-up time has elapsed, in order to allow oscillation to stabilize. After STOP
mode has been cleared, either NORMAL mode or SLOW mode can be selected
using the SYSCR0<RSYSCK> register. Therefore, <RSYSCK>, <RXEN> and
<RXTEN> must be set see the sample warm-up times in Table 3.3.6.
an interrupt.
X1
When STOP mode is selected, all internal circuits stop, including the internal
After STOP mode has been cleared system clock output starts when the
Figure 3.3.8 illustrates the timing for clearance of the STOP mode halt state by
01 (2
9.0 µ s
7.8 ms
Data
8
)
91C016-34
SYSCR2<WUPTM1:0>
STOP
mode
500
10 (2
0.607 ms
Warm-up
time
14
ms
)
at f
OSCH
= 27 MHz, fs = 32.768 kHz
2000
11 (2
2.427 ms
16
ms
)
TMP91C016
2008-02-20
Data