TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 191

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

LCDSAL
(0360H)
LCDSAH
(0361H)
LCDSIZE
(0362H)
LCDCTL
(0363H)
3.13.3
Note 1: There is a limitation about to set LCDSAH and LCDSAL start address.
Note 2: Initial incriminator’s address (LSB 14 bits) for LCDC DMA is 0000 (Hex).
Note: Bit mode can not select in 240 common number.
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Control Registers
It prohibit to set A13 carry to A14 by all 1-frame data transmit.
(SR, RAM
mode)
0: OFF
1: ON
DOFF
SR mode
LCD common number (SR mode)
LCDON
SAL15
SAL23
0000: 64
0001: 68
0010: 80
0011: 100
0100: 120
COM3
R/W
R/W
R/W
R/W
Display memory address (Low: A15 to A12)
Ex.: In case 240 (Row) × 360 (Column): 2a30 bytes
7
7
7
7
0
0
0
0
Start address of LCDC: SAL15 to SAL12 = 0000 or 0001;
Always
write 0
SAL14
SAL22
COM2
R/W
R/W
R/W
R/W
0101: 128
0110: 144
0111: 160
1000: 200
1001: 240
6
6
6
6
0
0
0
0
-
Always
write 0
SAL13
SAL21
COM1
Display memory address (High: A23 to A16)
R/W
R/W
R/W
R/W
5
5
5
5
0
0
0
Other: Reserved
0
-
LCDSIZE Register
LCDSAH Register
LCDSAL Register
LCDCTL Register
91C016-189
Data bus width
00: 8 bits (Byte mode)
01: 4 bits (
10: 1 bit (Bit mode)
(SR mode)
SAL12
SAL20
COM0
BUS1
R/W
R/W
R/W
R/W
4
4
4
4
0
0
0
0
SR mode
Nibble mode
LCD segment number (SR mode)
0000: 32
0001: 64
0010: 80
0011: 120
0100: 128
SAL19
SEG3
BUS0
R/W
R/W
R/W
3
3
3
3
0
0
0
)
Setting
direct
RAM
0: OFF
1: ON
MMULCD
Always
write 0
SAL18
SEG2
R/W
R/W
R/W
R/W
0101: 160
0110: 240
0111: 320
1000: 360
Other: Reserved
2
0
2
2
2
–
0
0
0
Setting bit
8 for f
Always
write 0
SAL17
SEG1
FP8
R/W
R/W
R/W
R/W
1
0
1
1
1
0
0
0
–
FP
Start
control
(SR mode)
0: Stop
1: Start
Mode
select
0: RAM
1: SR
START
MODE
SAL16
SEG0
R/W
R/W
R/W
R/W
TMP91C016
0
0
0
0
0
0
0
0
2008-02-20