TMP91xy16FG Toshiba, TMP91xy16FG Datasheet - Page 150

• Manufacturer Part Number: TMP91xy16FG
• Manufacturer: Toshiba

Specifications of TMP91xy16FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: -
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 31
• Power Supply Voltage(v): 2.7 to 3.6

Timing
transmission data
SCLK1 output
(<SCLKS>=0
Rising edge mode)
ITX1C
(INTTX1
Interrupt request)
SCLK1 output
(<SCLKS>=1
Falling edge mode)
TXD1
to
(INTTX1
Interrupt request)
TXD1
SCLK1input
(<SCLKS> = 0
Rising edge mode)
SCLK1 input
(<SCLKS> = 1
Falling edge mode)
ITX1C
write
Figure 3.9.19 Transmitting Operation in I/O Interface Mode (SCLK1 output mode)
Figure 3.9.20 Transmitting Operation in I/O Interface Mode (SCLK1 input mode)
a.
Transmission
TXD1 and SCLK1 pins respectively each time the CPU writes the data to the
transmission buffer. When all data is output, INTES1<ITX1C> will be set to
generate the INTTX1 interrupt.
input becomes active after the data has been written to the transmission buffer by
the CPU.
interrupt.
In SCLK output mode 8-bit data and a synchronous clock are output on the
In SCLK input mode, 8-bit data is output on the TXD1 pin when the SCLK1
When all data is output, INTES1<ITX1C> will be set to generate INTTX1
Bit0
Bit0
91C016-148
Bit1
Bit1
Bit5
Bit6
Bit6
Bit7
Bit7
TMP91C016
2008-02-20