ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 58
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
74
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5.13.2
5.13.3
5.13.4
8331A–AVR–07/11
INTFLAGS – DMA Interrupt Status Register
STATUS – DMA Status Register
TEMPL – DMA Temporary Register Low
• Bit 7:4 – CHnERRIF[3:0]: DMA Channel n Error Interrupt Flag
If an error condition is detected on DMA channel n, the CHnERRIF flag will be set. Writing a one
to this bit location will clear the flag.
• Bit 3:0 – CHnTRNFIF[3:0]: DMA Channel n Transaction Complete Interrupt Flag
When a transaction on channel n has been completed, the CHnTRFIF flag will be set. If unlim-
ited repeat count is enabled, this flag is read as one after each block transfer. Writing a one to
this bit location will clear the flag.
• Bit 7:4 – CHnBUSY[3:0]: DMA Channel Busy
When channel n starts a DMA transaction, the CHnBUSY flag will be read as one. This flag is
automatically cleared when the DMA channel is disabled, when the channel n transaction com-
plete interrupt flag is set, or if the DMA channel n error interrupt flag is set.
• Bit 3:0 – CHnPEND[3:0]: DMA Channel Pending
If a block transfer is pending on DMA channel n, the CHnPEND flag will be read as one. This
flag is automatically cleared when the block transfer starts or if the transfer is aborted.
• Bit 7:0 – TEMP[7:0]: DMA Temporary Register 0
This register is used when reading 16- and 24-bit registers in the DMA controller. Byte 1 of the
16/24-bit register is stored here when it is written by the CPU. Byte 1 of the 16/24-bit register is
stored when byte 0 is read by the CPU. This register can also be read and written from the user
software.
Reading and writing 16- and 24-bit registers requires special attention. For details, refer to
”Accessing 16-bit Registers” on page
Bit
+0x03
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
CH3ERRIF
CH3BUSY
R/W
7
0
R/W
7
R
0
7
0
CH2ERRIF
CH2BUSY
R/W
6
0
R/W
R
6
0
6
0
CH1ERRIF
CH1BUSY
R/W
5
0
R/W
R
5
0
5
0
12.
CH0ERRIF
R/W
CH0BUSY
4
0
R/W
R
4
0
4
0
TEMP[7:0]
CH3TRNFIF
CH3PEND
R/W
3
0
Atmel AVR XMEGA AU
R/W
R
3
0
3
0
CH2TRNFIF
CH2PEND
R/W
2
0
R/W
R
2
0
2
0
CH1TRNFIF
CH1PEND
R/W
R/W
1
0
R
1
0
1
0
CH0TRNFIF
CH0PEND
R/W
R/W
0
0
R
0
0
0
0
INTFLAGS
STATUS
TEMPL
58
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