ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 128
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
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ATxmega64A4U-U
Manufacturer:
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11.6
11.7
11.7.1
8331B–AVR–06/11
Configuration Protection and Lock
Registers Description
CTRL – Watchdog Timer Control Register
The WDT is designed with two security mechanisms to avoid unintentional changes to the WDT
settings.
The first mechanism is the configuration change protection mechanism, employing a timed write
procedure for changing the WDT control registers. In addition, for the new configuration to be
written to the control registers, the register’s change enable bit must be written at the same time.
The second mechanism locks the configuration by setting the WDT lock fuse. When this fuse is
set, the watchdog time control register cannot be changed; hence, the WDT cannot be disabled
from software. After system reset, the WDT will resume at the configured operation. When the
WDT lock fuse is programmed, the window mode timeout period cannot be changed, but the
window mode itself can still be enabled or disabled.
• Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 5:2 – PER[3:0]: Watchdog Timeout Period
These bits determine the watchdog timeout period as a number of 1kHz ULP oscillator cycles. In
window mode operation, these bits define the open window period. The different typical timeout
periods are found in
period (WDP) fuses, which are loaded at power-on.
In order to change these bits, the CEN bit must be written to 1 at the same time. These bits are
protected by the configuration change protection mechanism. For a detailed description, refer to
”Configuration Change Protection” on page
Table 11-1.
Bit
+0x00
Read/Write
(unlocked)
Read/Write
(locked)
Initial Value
(x = fuse)
PER[3:0]
0000
0001
0010
0011
0100
0101
Watchdog timeout periods .
R
R
7
–
0
Table
R
R
6
–
0
11-1. The initial values of these bits are set by the watchdog timeout
Group Configuration
R/W
R
X
5
128CLK
256CLK
16CLK
32CLK
64CLK
8CLK
R/W
R
4
X
12.
PER[3:0]
ATMEL CONFIDENTIAL
R/W
Atmel AVR XMEGA AU
R
X
3
R/W
R
2
X
Typical Timeout Periods
ENABLE
R/W
R
X
1
0.128s
0.256s
16ms
32ms
64ms
8ms
CEN
R/W
R
0
0
CTRL
128
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