ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 183
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
74
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14.12.9
8331A–AVR–07/11
CTRLGCLR/CTRLGSET – Control Register G Clear/Set
• Bit 3:2 – CMD[1:0]: Command
These bits can be used for software control of update, restart, and reset of the timer/counter.
The command bits are always read as zero.
Table 14-8.
• Bit 1 – LUPD: Lock Update:
When this bit is set, no update of the buffered registers is performed, even though an UPDATE
condition has occurred. Locking the update ensures that all buffers, including DTI buffers, are
valid before an update is performed.
This bit has no effect when input capture operation is enabled.
• Bit 0 – DIR: Counter Direction:
When zero, this bit indicates that the counter is counting up (incrementing). A one indicates that
the counter is in the down-counting (decrementing) state.
Normally this bit is controlled in hardware by the waveform generation mode or by event actions,
but this bit can also be changed from software.
Refer to
on how to access this type of status register.
• Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4:1 – CCxBV: Compare or Capture x Buffer Valid
These bits are set when a new value is written to the corresponding CCxBUF register. These
bits are automatically cleared on an UPDATE condition.
Note that when input capture operation is used, this bit is set on a capture event and cleared if
the corresponding CCxIF is cleared.
• Bit 0 – PERBV: Period Buffer Valid
This bit is set when a new value is written to the PERBUF register. This bit is automatically
cleared on an UPDATE condition.
Bit
+0x0A/ +0x0B
Read/Write
Initial Value
CMD
00
01
10
11
”CTRLFCLR/CTRLFSET – Control Register F Clear/Set” on page 182
Command selections
7
–
R
0
Group Configuration
RESTART
R
6
–
0
UPDATE
RESET
NONE
R
5
–
0
CCDBV
R/W
4
0
Command Action
None
Force update
Force restart
Force hard reset (ignored if T/C is not in OFFstate)
CCCBV
R/W
3
0
Atmel AVR XMEGA AU
CCBBV
R/W
2
0
CCABV
R/W
1
0
PERBV
R/W
0
0
for information
CTRLGCLR/SET
183
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