ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 209
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Manufacturer
Quantity
Price
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16.7.4
8331A–AVR–07/11
STATUS – Status Register
• Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4 – FDDBD: Fault Detection on Debug Break Detection
By default, when this bit is cleared and fault protection is enabled, and OCD break request is
treated as a fault. When this bit is set, an OCD break request will not trigger a fault condition.
• Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 2 – FDMODE: Fault Detection Restart Mode
This bit sets the fault protection restart mode. When this bit is cleared, latched mode is used,
and when it is set, cycle-by-cycle mode is used.
In latched mode, the waveform output will remain in the fault state until the fault condition is no
longer active and the FDF has been cleared by software. When both conditions are met, the
waveform output will return to normal operation at the next UPDATE condition.
In cycle-by-cycle mode, the waveform output will remain in the fault state until the fault condition
is no longer active. When this condition is met, the waveform output will return to normal opera-
tion at the next UPDATE condition
• Bit 1:0 – FDACT[1:0]: Fault Detection Action
These bits define the action performed, according to
detected.
Table 16-1.
• Bit 7:3 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
Bit
+0x04
Read/Write
Initial Value
FDACT[1:0]
00
01
10
11
Fault actions
R
7
–
0
Group Configuration
R
6
–
0
CLEARDIR
NONE
R
5
–
0
.
R
4
–
0
Description
None (fault protection disabled)
Reserved
Reserved
Clear all direction (DIR) bits which correspond to the
enabled DTI channel(s); i.e., tri-state the outputs
R
3
–
0
Atmel AVR XMEGA AU
Table
FDF
R/W
2
0
16-1, when a fault condition is
DTHSBUFV
R/W
1
0
DTLSBUFV
R/W
0
0
STATUS
209
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