ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 268
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
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21.5.1.2
21.5.1.3
21.5.1.4
21.5.2
21.5.3
21.6
8331A–AVR–07/11
TWI Slave Operation
Transmitting Data Packets
Receiving Data Packets
Case M2: Address packet transmit complete - Address not acknowledged by slave
Case M3: Address packet transmit complete - Direction bit cleared
Case M4: Address packet transmit complete - Direction bit set
If no slave device responds to the address, the master write interrupt flag and the master
received acknowledge flag are set. The clock hold is active at this point, preventing further activ-
ity on the bus.
If the master receives an ACK from the slave, the master write interrupt flag is set and the mas-
ter received acknowledge flag is cleared. The clock hold is active at this point, preventing further
activity on the bus.
If the master receives an ACK from the slave, the master proceeds to receive the next byte of
data from the slave. When the first data byte is received, the master read interrupt flag is set and
the master received acknowledge flag is cleared. The clock hold is active at this point, prevent-
ing further activity on the bus.
Assuming case M3 above, the master can start transmitting data by writing to the master data
register. If the transfer was successful, the slave will signal with ACK. The master write interrupt
flag is set, the master received acknowledge flag is cleared, and the master can prepare new
data to send. During data transfer, the master is continuously monitoring the bus for collisions.
The received acknowledge flag must be checked by software for each data packet transmitted
before the next data packet can be transferred. The master is not allowed to continue transmit-
ting data if the slave signals a NACK.
If a collision is detected and the master loses arbitration during transfer, the arbitration lost flag is
set.
Assuming case M4 above, the master has already received one byte from the slave. The master
read interrupt flag is set, and the master must prepare to receive new data. The master must
respond to each byte with ACK or NACK. Indicating a NACK might not be successfully exe-
cuted, as arbitration can be lost during the transmission. If a collision is detected, the master
loses arbitration and the arbitration lost flag is set.
The TWI slave is byte-oriented with optional interrupts after each byte. There are separate slave
data and address/stop interrupts. Interrupt flags can also be used for polled operation. There are
dedicated status flags for indicating ACK/NACK received, clock hold, collision, bus error, and
read/write direction.
When an interrupt flag is set, the SCL line is forced low. This will give the slave time to respond
or handle data, and will in most cases require software interaction.
slave operation. The diamond shapes symbols (SW) indicate where software interaction is
required.
Atmel AVR XMEGA AU
Figure
21-13. shows the TWI
268
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