ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 28
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
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Quantity:
29 000
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Manufacturer:
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4.15.10
4.15.11
8331A–AVR–07/11
INTCTRL – Nonvolatile Memory Interrupt Control Register
STATUS – Nonvolatile Memory Status Register
• Bit 0 – SPMLOCK: SPM Locked
This bit can be written to prevent all further self-programming. The bit is cleared at reset, and
cannot be cleared from software. This bit is protected by the configuration change protection
(CCP) mechanism.Refer to
CCP.
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 – SPMLVL[1:0]: SPM Ready Interrupt Level
These bits enable the interrupt and select the interrupt level, as described in
grammable Multilevel Interrupt Controller” on page
triggered the BUSY flag in the STATUS is set to zero. Thus, the interrupt should not be enabled
before triggering an NVM command, as the NVMBUSY flag will not be set before the NVM com-
mand is triggered. The interrupt should be disabled in the interrupt handler.
• Bit 1:0 – EELVL[1:0]: EEPROM Ready Interrupt Level
These bits enable the EEPROM ready interrupt and select the interrupt level, as described in
”Interrupts and Programmable Multilevel Interrupt Controller” on page
rupt, and will be triggered when the BUSY flag in the STATUS is set to . Thus, the interrupt
should not be enabled before triggering an NVM command, as the BUSY flag wont be set before
the NVM command is triggered. The interrupt should be disabled in the interrupt handler.
• Bit 7 – NVMBUSY: Nonvolatile Memory Busy
The NVMBUSY flag indicates if the NVM is being programmed. Once an operation is started,
this flag is set and remains set until the operation is completed. The NVMBUSY flag is automati-
cally cleared when the operation is finished.
• Bit 6 – FBUSY: Flash Busy
The FBUSY flag indicates if a flash programming operation is initiated. Once an operation is
started the FBUSY flag is set and the application section cannot be accessed. The FBUSY flag
is automatically cleared when the operation is finished.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x0D
Read/Write
Initial Value
NVMBUSY
R
7
–
0
R
7
0
FBUSY
R
6
–
0
R
6
0
”Configuration Change Protection” on page 12
R
5
–
0
5
–
R
0
R
4
–
0
R
4
–
0
Atmel AVR XMEGA AU
R
3
–
0
R/W
132. This is a level interrupt, and will be
3
0
SPMLVL[1:0]
R
2
–
0
R/W
2
0
EELOAD
1
R
0
R/W
132. This is a level inter-
1
0
EELVL[1:0]
”Interrupts and Pro-
for details on the
FLOAD
R/W
R
0
0
0
0
INTCTRL
STATUS
28
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