ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 299
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
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23.8.2
23.8.3
8331A–AVR–07/11
Asynchronous Data Recovery
Asynchronous Operational Range
The data recovery unit uses sixteen samples in normal mode and eight samples in double speed
mode for each bit.
Figure 23-7. Sampling of data and parity bits.
As for start bit detection, an identical majority voting technique is used on the three center sam-
ples for deciding of the logic level of the received bit. The process is repeated for each bit until a
complete frame is received. It includes the first stop bit, but excludes additional ones. If the sam-
pled stop bit is a 0 value, the frame error (FERR) flag will be set.
Figure 23-8 on page 299
beginning of the next frame's start bit.
Figure 23-8. Stop bit and next start bit sampling.
A new high-to-low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For normal speed mode, the first low level sample can be at the
point marked (A) in Stop Bit Sampling and Next Start Bit Sampling. For double speed mode, the
first low level must be delayed to point (B). Point (C) marks a stop bit of full length at nominal
baud rate. The early start bit detection influences the operational range of the receiver.
The operational range of the receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If an external transmitter is sending using bit rates
that are too fast or too slow, or if the internally generated baud rate of the receiver does not
match the external source’s base frequency, the receiver will not be able to synchronize the
frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
(CLK2X = 0)
(CLK2X = 1)
(CLK2X = 0)
(CLK2X = 1)
Sample
Sample
Sample
Sample
RxD
RxD
Figure 23-7 on page 299
1
1
1
1
2
2
shows the sampling of the stop bit in relation to the earliest possible
3
2
3
2
4
4
5
3
5
3
6
6
shows the sampling process of data and parity bits.
7
4
7
4
8
8
STOP 1
BIT n
Atmel AVR XMEGA AU
9
5
9
5
10
10
(A)
0/1
11
6
6
0/1
12
(B)
0/1
0/1
13
7
14
15
8
16
(C)
1
1
299
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