ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 269
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
74
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Figure 21-13. TWI slave operation.
21.6.1
21.6.1.1
21.6.1.2
8331A–AVR–07/11
S1
S2
SW
Sn
Driver software
The master provides data
on the bus
Slave provides data on
the bus
Diagram connections
Receiving Address Packets
S3
S
Case S1: Address packet accepted - Direction bit set
Case S2: Address packet accepted - Direction bit cleared
ADDRESS
The number of interrupts generated is kept to a minimum by automatic handling of most condi-
tions. Quick command can be enabled to auto-trigger operations and reduce software
complexity.
Promiscuous mode can be enabled to allow the slave to respond to all received addresses.
When the TWI slave is properly configured, it will wait for a START condition to be detected.
When this happens, the successive address byte will be received and checked by the address
match logic, and the slave will ACK a correct address. If the received address is not a match, the
slave will not acknowledge the address, and will wait for a new START condition.
The slave address/stop interrupt flag is set when a START condition succeeded by a valid
address byte is detected. A general call address will also set the interrupt flag.
A START condition immediately followed by a STOP condition is an illegal operation, and the
bus error flag is set.
The R/W direction flag reflects the direction bit received with the address. This can be read by
software to determine the type of operation currently in progress.
Depending on the R/W direction bit and bus condition, one of four distinct cases (S1 to S4)
arises following the address packet. The different cases must be handled in software.
If the R/W direction flag is set, this indicates a master read operation. The SCL line is forced low
by the slave, stretching the bus clock. If ACK is sent by the slave, the slave hardware will set the
data interrupt flag indicating data is needed for transmit. Data, repeated START, or STOP can
be received after this. If NACK is sent by the slave, the slave will wait for a new START condition
and address match.
If the R/W direction flag is cleared, this indicates a master write operation. The SCL line is forced
low, stretching the bus clock. If ACK is sent by the slave, the slave will wait for data to be
Interrupt on STOP
Condition Enabled
SLAVE ADDRESS INTERRUPT
Collision
(SMBus)
W
R
SW
SW
SW
SW
Release
Hold
A/A
A
A
A
S1
S1
S1
Sr
P
S2
S3
DATA
Atmel AVR XMEGA AU
SLAVE DATA INTERRUPT
SW
SW
A/A
Sr
P
S2
S3
DATA
A/A
269
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