ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 407
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
74
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31.5
31.5.1
8331A–AVR–07/11
Boundary Scan Chain
Scanning the Port Pins
The active states are:
The boundary scan chain has the capability of driving and observing the logic levels on the I/O
pins. To ensure a predictable device behavior during and after the EXTEST, CLAMP, and
HIGHZ instructions, the device is automatically put in reset. During active reset, the external
oscillators, analog modules, and non-default port pin settings (like pull-up/down, bus-keeper,
wired-AND/OR) are disabled. It should be noted that the current device and port pin state are
unaffected by the SAMPLE and PRELOAD instructions.
Figure 31-2 on page 407
This cell is able to control and observe both pin direction and pin value via a two-stage shift reg-
ister. When no alternate port function is present, output control corresponds to the DIR register
value, output data corresponds to the OUT register value, and input data corresponds to the IN
register value (tapped before the input inverter and input synchronizer). Mode represents either
an active CLAMP or EXTEST instruction, while shift DR is set when the TAP controller is in its
shift DR state.
Figure 31-2. Bidirectional boundary scan cell.
• Capture DR: Parallel data from the PDI are sampled into the PDICOM data register
• Shift DR: The PDICOM data register is shifted by the TCK input
• Update DR: Commands or operands are parallel-latched from the PDICOM data register into
the PDI
Output Data
Output Control
Input Data
(IN)
(IN)
(DIR)
shows the boundary scan cell used for all the bidirectional port pins.
Mode
0
1
0
1
From last cell Clock DR
Shift DR
0
1
0
1
Atmel AVR XMEGA AU
To next cell
D
D Q
Update DR
Q
D
D Q
Q
En
Pn
407
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