ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 19
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
74
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4. Memories
4.1
4.2
8331A–AVR–07/11
Features
Overview
•
•
•
•
This section describes the different memories in XMEGA AU devices. The AVR architecture has
two main memory spaces, the program memory and the data memory. Executable code can
reside only in the program memory, while data can be stored in the program memory and the
data memory. The data memory includes the internal SRAM EEPROM for nonvolatile data stor-
age. All memory spaces are linear and require no memory bank switching. Nonvolatile memory
Flash program memory
Data memory
Production signature row memory for factory programmed data
User signature row
– One linear address space
– In-system programmable
– Self-programming and boot loader support
– Application section for application code
– Application table section for application code or data storage
– Boot section for application code or bootloader code
– Separate read/write protection lock bits for all sections
– Built in fast CRC check of a selectable flash program memory section
– One linear address space
– Single-cycle access from CPU
– SRAM
– EEPROM
– I/O memory
– External memory support
– Bus arbitration
– Separate buses for SRAM, EEPROM, I/O memory, and external memory access
Byte and page accessible
Optional memory mapping for direct load and store
Configuration and status registers for all peripherals and modules
16 bit-accessible general purpose registers for global variables or flags
SRAM
SDRAM
Memory mapped external hardware
Safe and deterministic handling of priority between CPU, DMA controller, and other bus
masters
Simultaneous bus access for CPU and DMA controller
ID for each microcontroller device type
Serial number for each device
Calibration bytes for factory calibrated peripherals
One flash page in size
Can be read and written from software
Content is kept after chip erase
Atmel AVR XMEGA AU
19
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