ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 263
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
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21.3.7
8331A–AVR–07/11
Clock and Clock Stretching
Figure 21-5. Master write transaction.
Assuming the slave acknowledges the address, the master can start transmitting data (DATA)
and the slave will ACK or NACK (A/A) each byte. If no data packets are to be transmitted, the
master terminates the transaction by issuing a STOP condition (P) directly after the address
packet. There are no limitations to the number of data packets that can be transferred. If the
slave signals a NACK to the data, the master must assume that the slave cannot receive any
more data and terminate the transaction.
Figure 21-6 on page 263
action by issuing a START condition followed by an address packet with the direction bit set to
one (ADDRESS+R). The addressed slave must acknowledge the address for the master to be
allowed to continue the transaction.
Figure 21-6. Master read transaction.
Assuming the slave acknowledges the address, the master can start receiving data from the
slave. There are no limitations to the number of data packets that can be transferred. The slave
transmits the data while the master signals ACK or NACK after each data byte. The master ter-
minates the transfer with a NACK before issuing a STOP condition.
Figure 21-7
and write transactions separated by repeated START conditions (Sr).
Figure 21-7. Combined Transaction.
All devices connected to the bus are allowed to stretch the low period of the clock to slow down
the overall clock frequency or to insert wait states while processing data. A device that needs to
stretch the clock can do this by holding/forcing the SCL line low after it detects a low level on the
line.
S
S
S
ADDRESS
Address Packet #1
ADDRESS
ADDRESS
illustrates a combined transaction. A combined transaction consists of several read
Address Packet
Address Packet
R/W
A
Direction
illustrates the master read transaction. The master initiates the trans-
W
R
N Data Packets
DATA
A
A
Transaction
Transaction
A/A
DATA
DATA
Data Packet
Data Packet
Transaction
Sr
Atmel AVR XMEGA AU
ADDRESS
Address Packet #2
N data packets
N data packets
A
A
R/W
A
Direction
DATA
DATA
M Data Packets
DATA
A/A
A
A/A
P
P
263
P
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