ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 100
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
74
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7.11.3
7.11.4
8331A–AVR–07/11
CALB – DFLL Calibration Register B
COMP1 – DFLL Compare Resgister Byte 1
• Bit 7 – Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
• Bit 6:0 – CALA[6:0]: DFLL Calibration Bits
These bits hold the part of the oscillator calibration value that is used for automatic runtime cali-
bration. A factory-calibrated value is loaded from the signature row of the device and written to
this register during reset, giving an oscillator frequency approximate to the nominal frequency for
the oscillator. The bits cannot be written when the DFLL is enabled.
• Bit 7:6 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 5:0 – CALB[5:0]: DFLL Calibration bits
These bits hold the part of the oscillator calibration value that is used to select the oscillator fre-
quency. A factory-calibrated value is loaded from the signature row of the device and written to
this register during reset, giving an oscillator frequency approximate to the nominal frequency for
the oscillator. These bits are not changed during automatic run-time calibration of the oscillator.
The bits cannot be written when the DFLL is enabled. When calibrating to a frequency different
from the default, the CALA bits should be set to a middle value to maximize the range for the
DFLL.
The COMP1 and COMP2 register pair represent the frequency ratio between the oscillator and
the reference clock. The initial value for these registers is the ratio between the internal oscillator
frequency and a 1.024kHz reference.
• Bit 7:0 – COMP1[7:0]: Compare Register Byte 1
These bits hold byte 1 of the 16-bit compare register.
Bit
+0x05
Read/Write
Initial Value
Bit
+0x03
Read/Write
Initial Value
R/W
R/W
7
0
7
–
0
R/W
R/W
6
0
6
–
0
R/W
R/W
5
0
5
x
R/W
R/W
4
0
4
x
COMP[7:0]
R/W
R/W
3
0
Atmel AVR XMEGA AU
3
x
CALB[5:0]
R/W
R/W
2
0
2
x
R/W
R/W
1
0
1
x
R/W
R/W
0
0
0
x
COMP1
CALB
100
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