ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 348
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
74
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27.11 Register Description
27.11.1
8331A–AVR–07/11
CTRLA – Control Register A
Table 27-19. SDRAM Exit Self Refresh Delay settings
• Bit 2:0 – ROWCOLDLY[2:0]: SDRAM Row to Column Delay
This field defines the delay between an ACTIVE command and a Read/Write command as a
number of Clk
Table 27-20. SDRAM Row Column Delay settings
• Bit 7 – Reserved
This bit is reserved and will always be read as zero.
• Bit 6:2 – ASIZE[4:0]: Address Size
These bits select the address size for the Chip Select. This is the size of the block above the
base address.
Table 27-21. Address size encoding
Bit
+0x00
Read/Write
Initial Value
ASIZE[4:0]
00000
00001
00010
00011
00100
ROWCOLDLY[2:0]
ESRDLY[2:0]
–
101
110
111
000
001
010
011
100
101
110
111
EBI Chip Select
PER2
R
7
–
0
cycles, according to
R/W
6
0
Group Configuration
5CLK
6CLK
7CLK
Group Configuration
0CLK
1CLK
2CLK
3CLK
4CLK
5CLK
6CLK
7CLK
Group Configuration
256B
512B
1K
2K
4K
R/W
5
0
ASIZE[4:0]
R/W
Table 27-20 on page
4
0
Description
5 Clk
6 Clk
7 Clk
Description
0 Clk
1 Clk
2 Clk
3 Clk
4 Clk
5 Clk
6 Clk
7 Clk
Address Size
256 Bytes
512 Bytes
1K Bytes
2K Bytes
4K Bytes
R/W
3
0
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
Atmel AVR XMEGA AU
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
R/W
2
0
348.
Address Lines Compared
ADDR[23:8]
ADDR[23:9]
ADDR[23:10]
ADDR[23:11]
ADDR[23:12]
R/W
1
0
MODE[1:0]
R/W
0
0
CTRLA
348
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