ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 295
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
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23.4
8331A–AVR–07/11
Frame Formats
on page
receiver and transmitter.
Table 23-2.
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge
of a clock cycle.
Figure 23-4. UCPHA and INVEN data transfer timing diagrams.
Data transfer is frame based, where a serial frame consists of one character of data bits with
synchronization bits (start and stop bits) and an optional parity bit for error checking. Note that
this does not apply to master SPI operation (See
USART accepts all combinations of the following as valid frame formats:
A frame starts with the start bit, followed by all the data bits (least-significant bit first and most-
significant bit last). If enabled, the parity bit is inserted after the data bits, before the first stop bit.
One frame can be directly followed by a start bit and a new frame, or the communication line can
return to the idle (high) state.
frame formats. Bits inside brackets are optional.
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even, or odd parity bit
• 1 or 2 stop bits
SPI Mode
0
1
2
3
295. Changing the setting of any of these bits during transmission will corrupt both the
Data setup (TXD)
Data sample (RXD)
XCK
XCK
Data setup (TXD)
Data sample (RXD)
INVEN and UCPHA functionality.
INVEN
0
0
1
1
UCPOL=0
Figure 23-5 on page 296
UCPHA
0
1
0
1
Leading Edge
Rising, sample
Rising, setup
Falling, sample
Falling, setup
Atmel AVR XMEGA AU
”SPI Frame Formats” on page
Data setup (TXD)
Data setup (TXD)
XCK
Data sample (RXD)
XCK
Data sample (RXD)
illustrates the possible combinations of
Trailing Edge
Falling, setup
Falling, sample
Rising, setup
Rising, sample
UCPOL=1
296). The
295
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