ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 132
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
74
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12. Interrupts and Programmable Multilevel Interrupt Controller
12.1
12.2
12.3
8331A–AVR–07/11
Features
Overview
Operation
•
•
•
•
Interrupts signal a change of state in peripherals, and this can be used to alter program execu-
tion. Peripherals can have one or more interrupts, and all are individually enabled and
configured. When an interrupt is enabled and configured, it will generate an interrupt request
when the interrupt condition is present. The programmable multilevel interrupt controller (PMIC)
controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowl-
edged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt
handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium,
and high. Interrupts are prioritized according to their level and their interrupt vector address.
Medium-level interrupts will interrupt low-level interrupt handlers. High-level interrupts will inter-
rupt both medium- and low-level interrupt handlers. Within each level, the interrupt priority is
decided from the interrupt vector address, where the lowest interrupt vector address has the
highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to
ensure that all interrupts are serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical
functions.
If a boot loader is used, it is possible to move the interrupt vectors from the application section to
the boot loader section so interrupts can also be used and executed during self-programming.
Interrupts must be globally enabled for any interrupts to be generated. This is done by setting
the global interrupt enable ( I ) bit in the CPU status register. The I bit will not be cleared when an
interrupt is acknowledged. Each interrupt level must also be enabled before interrupts with the
corresponding level can be generated.
When an interrupt is enabled and the interrupt condition is present, the PMIC will receive the
interrupt request. Based on the interrupt level and interrupt priority of any ongoing interrupts, the
interrupt is either acknowledged or kept pending until it has priority. When the interrupt request
is acknowledged, the program counter is updated to point to the interrupt vector. The interrupt
vector is normally a jump to the interrupt handler; the software routine that handles the interrupt.
After returning from the interrupt handler, program execution continues from where it was before
the interrupt occurred. One instruction is always executed before any pending interrupt is
served.
Short and predictable interrupt response time
Separate interrupt configuration and vector address for each interrupt
Programmable multilevel interrupt controller
Interrupt vectors can be moved from the application section to the boot loader section
– Interrupt prioritizing according to level and vector address
– Three selectable interrupt levels for all interrupts: low, medium and high
– Selectable, round-robin priority scheme within low-level interrupts
– Non-maskable interrupts for critical functions
Atmel AVR XMEGA AU
132
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