ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 261
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
74
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21.3.1
21.3.2
8331A–AVR–07/11
Electrical Characteristics
START and STOP Conditions
Figure 21-2. Basic TWI transaction diagram topology for a 7-bit address bus .
The master provides the clock signal for the transaction, but a device connected to the bus is
allowed to stretch the low-level period of the clock to decrease the clock speed.
The TWI module in XMEGA devices follows the electrical specifications and timing of I
and SMBus. These specifications are not 100% compliant, and so to ensure correct behavior,
the inactive bus timeout period should be set in TWI master mode. Refer to
tion” on page 266
Two unique bus conditions are used for marking the beginning (START) and end (STOP) of a
transaction. The master issues a START condition (S) by indicating a high-to-low transition on
the SDA line while the SCL line is kept high. The master completes the transaction by issuing a
STOP condition (P), indicated by a low-to-high transition on the SDA line while SCL line is kept
high.
Figure 21-3. START and STOP conditions.
Multiple START conditions can be issued during a single transaction. A START condition that is
not directly following a STOP condition is called a repeated START condition (Sr).
SDA
SCL
SDA
SCL
S
The master provides data on the bus
The master or slave can provide data on the bus
The slave provides data on the bus
S
Condition
START
for more details.
ADDRESS
ADDRESS
S
6 ... 0
Address Packet
R/W
R/W
A
Direction
ACK
Data Packet #0
Transaction
DATA
DATA
7 ... 0
Atmel AVR XMEGA AU
ACK
A
Data Packet #1
DATA
DATA
7 ... 0
”TWI Master Opera-
ACK/NACK
Condition
A/A
STOP
P
P
P
2
C bus
261
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