ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 415
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A4U-AU
Manufacturer:
ON
Quantity:
29 000
Company:
Part Number:
ATxmega64A4U-U
Manufacturer:
ATMEL
Quantity:
74
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32.4
32.4.1
8331A–AVR–07/11
JTAG Physical
Enabling
Figure 32-8. Driving data out on the PDI_DATA using a bus keeper.
If the programmer and the PDI both drive the PDI_DATA line at the same time, drive contention
will occur, as illustrated in
clock cycles, the PDI is able to verify that the correct bit value is driven on the PDI_DATA line. If
the programmer is driving the PDI_DATA line to the opposite bit value to what the PDI expects,
a collision is detected.
Figure 32-9. Drive contention and collision detection on the PDI_DATA line.
As long as the PDI transmits alternating ones and zeros, collisions cannot be detected, because
the PDI output driver will be active all the time, preventing polling of the PDI_DATA line. How-
ever, the two stop bits should always be transmitted as ones within a single frame, enabling
collision detection at least once per frame.
The JTAG physical layer handles the basic low-level serial communication over four I/O lines,
TMS, TCK, TDI, and TDO. The JTAG physical layer includes BREAK detection, parity error
detection, and parity generation. For all generic JTAG details, refer to
Boundary Scan Interface” on page
The JTAGEN fuse must be programmed and the JTAG disable bit in the MCU control register
must be cleared to enable the JTAG interface. This is done by default. When the JTAG PDICOM
PDI_CLK
PDI Output
PDI_DATA
Programmer
Collision detect
Output enable
PDI Output
PDI_DATA
PDI_CLK
output
= Collision
1
1
Figure 32-9 on page
0
0
403.
X
1
415. Every time a bit value is kept for two or more
Atmel AVR XMEGA AU
1
1
0
X
0
”IEEE 1149.1 JTAG
1
1
1
415
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