DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 96

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Receive Free-Queue FIFO Enable (RFQFE). To enable the DMA to burst read descriptors from the free
queue, this bit must be set to 1. If this bit is set to 0, descriptors are read one at a time.
Bit 2/Receive Free-Queue Large Buffer FIFO Flush (RFQLF). When this bit is set to 1, the internal large
buffer free-queue FIFO is flushed (currently loaded free-queue descriptors are lost). This bit must be set to 0 for
proper operation.
Bit 3/Receive Free-Queue Small Buffer FIFO Flush (RFQSF). When this bit is set to 1, the internal small
buffer free-queue FIFO is flushed (currently loaded free-queue descriptors are lost). This bit must be set to 0 for
proper operation.
Bit 4/Receive Done-Queue FIFO Enable (RDQFE). See Section
Bit 5/Receive Done-Queue FIFO Flush (RDQF). See Section
Bits 8 to 10/Receive Done-Queue Status Bit Threshold Setting (RDQT0 to RDQT2). See Section
details.
0 = free-queue burst read disabled
1 = free-queue burst read enabled
0 = FIFO in normal operation
1 = FIFO is flushed
0 = FIFO in normal operation
1 = FIFO is flushed
n/a
n/a
15
7
0
0
RDMAQ
Receive DMA Queues Control
0780h
n/a
n/a
14
6
0
0
RDQF
n/a
13
5
0
0
RDQFE
96 of 183
n/a
12
4
0
0
RFQSF
9.2.4
n/a
11
3
0
0
9.2.4
for details.
for details.
RDQT2
RFQLF
10
2
0
0
RDQT1
n/a
1
0
9
0
RDQT0
RFQFE
0
0
8
0
9.2.4
for