DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 146

IC CTRLR HDLC 256-CHANNEL 256BGA

DS31256

Manufacturer Part Number
DS31256
Description
IC CTRLR HDLC 256-CHANNEL 256BGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS31256

Controller Type
HDLC Controller
Interface
Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
500mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Register Name:
Register Description:
Register Address:
MSB
Note: Read-only bits in the PLBM register are underlined; all other bits are read-write.
Bit 0/Memory Space Indicator (MSI). This read-only bit is forced to 0 to indicate that the local bus is mapped to
memory space.
Bits 1 and 2/Type 0 and Type 1. These read-only bits are forced to 00b to indicate that the local bus can be
mapped anywhere in the 32 bit address space.
Bit 3/Prefetchable (PF). This read-only bit is forced to 0 to indicate that prefetching is not supported by the
device for the local bus.
Bits 4 to 19/Base Address. These read-only bits are forced to 0 to indicate that the local bus requires 1MB of
memory space.
Bits 20 to 31/Base Address. These read/write bits define the location of the 1MB memory space that is mapped to
the local bus. These bits correspond to the most significant bits of the PCI address space.
Register Name:
Register Description:
Register Address:
MSB
Bits 0 to 7/Interrupt Line. These read/write bits indicate and store interrupt line routing information. The device
does not use this information, it is only posted here for the host to use.
Bits 8 to 15/Interrupt Pin. These read-only bits are forced to 01h to indicate that PINTA is used as an interrupt.
Bits 16 to 23/Minimum Grant. These read-only bits are forced to 0.
Bits 24 to 31/Maximum Latency. These read-only bits are forced to 0.
Base Address (Read Only/Set to 0h)
Base Address
PLBM
PCI Local Bus Memory Base Address Register
0x110h
PINTL1
PCI Interrupt Line and Pin/Minimum Grant/Maximum Latency Register 1
0x13Ch
Maximum Latency (Read Only/Set to 00h)
Maximum Grant (Read Only/Set to 00h)
Interrupt Pin (Read Only/Set to 01h)
146 of 183
Interrupt Line
Base Address
Base Address
PF
TYPE1
Base Address (Read Only/Set to 0h)
TYPE0
MSI
LSB
LSB

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