DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 78

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
block pointer RAM, the host should write this bit to 0. This causes the device to take the data that is currently
present in the RFBP register and write it to the channel location indicated by the BLKID bits. When the device
completes the write, the IAB is set to 0.
Note: The RFSBP is write-only memory. Once this register has been written to and the operation has started, the
DS31256 internal state machine changes the value in this memory.
Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set
to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is
ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the
write operation completes.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read only, all other bits are read-write.
Bits 0 to 9/Block Pointer (RBP0 to RBP9). These bits indicate which of the 10242 blocks is the next block in the
link-list chain. A block is not allowed to point to itself.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7)
Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive high-
watermark RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data
from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data
is ready to be read from the RFHWM register, the IAB bit is set to 0. When the host wishes to write data to the
internal receive high-watermark RAM, this bit should be written to 0 by the host. This causes the device to take
0000000000 (000h) = block 0 is the next linked block
0111111111 (1FFh) = block 511 is the next linked block
1111111111 (3FFh) = block 1023 is the next linked block
00000000 (00h) = HDLC channel number 1
11111111 (FFh) = HDLC channel number 256
HCID7
RBP7
IAB
n/a
15
15
7
7
0
RFBP
Receive FIFO Block Pointer
0914h
RFHWMIS
Receive FIFO High-Watermark Indirect Select
0920h
HCID6
IARW
RBP6
n/a
14
14
6
6
0
0
HCID5
RBP5
n/a
n/a
13
13
5
5
0
0
HCID4
RBP4
n/a
n/a
12
12
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4
4
0
0
HCID3
RBP3
n/a
n/a
11
11
3
3
0
0
HCID2
RBP2
n/a
n/a
10
10
2
2
0
0
HCID1
RBP9
RBP1
n/a
1
9
1
0
9
0
HCID0
RBP0
RBP8
n/a
0
8
0
8
0
0