DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 90

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.2.2 Packet Descriptors
A contiguous section of up to 65,536 quad dwords that make up the receive packet descriptors resides in
main memory. The receive packet descriptors are aligned on a quad dword basis and can be placed
anywhere in the 32-bit address space through the receive descriptor base address
buffer is associated with each descriptor. The data buffer can be up to 8188 Bytes long and must be a
contiguous section of main memory. The host can set two different data buffer sizes through the receive
large buffer size (RLBS) and the receive small buffer size (RSBS) registers (Section 9.2.1). If an
incoming packet requires more space than the data buffer allows, packet descriptors are link-listed
together by the DMA to provide a chain of data buffers.
descriptors were linked together for an incoming packet on HDLC channel 2.
example. Channel 9 only required a single data buffer and therefore only one packet descriptor was used.
Packet descriptors can be either free (available for use by the DMA) or used (currently contain data that
needs to be processed by the host). The free-queue descriptors point to the free-packet descriptors. The
done-queue descriptors point to the used-packet descriptors.
Table 9-C. Receive Descriptor Address Storage
Figure 9-3. Receive Descriptor Example
Receive Descriptor Base Address 0 (lower word)
Receive Descriptor Base Address 1 (upper word)
Free-Queue Descriptor
Address
Done-Queue Descriptor Pointer
REGISTER
Descriptors
Maximum of 65,536
Base + FFFD0h
Base + FFFF0h
Base + 00h
Base + 10h
Base + 20h
Base + 30h
Base + 40h
Base + 50h
Base + 60h
Base + 70h
Base + 80h
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RDBA0
RDBA1
NAME
Channel 9 Single Buffer Descriptor
Channel 2 Second Buffer Descriptor
Channel 2 First Buffer Descriptor
Channel 2 Last Buffer Descriptor
Figure 9-3
Free Descriptor
Free Descriptor
Free Descriptor
Free Descriptor
Free Descriptor
Free Descriptor
Free Descriptor
shows an example of how three
ADDRESS
0750h
0754h
Figure 9-2
(Table
shows a similar
9-C). A data