DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 123

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

When enabled through the transmit done-queue FIFO-enable (TDQFE) bit, the done-queue FIFO does
not write to the done queue until it reaches the high watermark. When the done-queue FIFO reaches the
high watermark (which is six descriptors), it attempts to empty the done-queue FIFO by burst writing to
the done queue. Before it writes to the done queue, it checks (by examining the transmit done-queue host
read pointer) to ensure the done queue has enough room to empty. If the done queue does not have
enough room, then it only burst writes enough descriptors to keep from overflowing. If the FIFO detects
that there is no room for any descriptors to be written, then it sets the status bit for transmit DMA done-
queue write error (TDQWE) in the SDMA and it does not write to the done queue nor does it increment
the write pointer. In such a scenario, information on transmitted packets is lost and unrecoverable. If the
done-queue FIFO can write descriptors to the done queue, then it burst writes them, increments the write
pointer, and sets the status bit for transmit DMA done-queue write (TDQW) in the SDMA. See Section
for more details about status bits.
Done-Queue FIFO Flush Timer
To ensure the done-queue FIFO gets flushed to the done queue on a regular basis, the transmit done-
queue FIFO flush timer (TDQFFT) is used by the DMA to determine the maximum wait time in between
writes. The TDQFFT is a 16-bit programmable counter that is decremented every PCLK divided by 256.
It is only monitored by the DMA when the transmit done-queue FIFO is enabled (TDQFE = 1). For a
33MHz PCLK, the timer is decremented every 7.76µs. For a 25MHz clock, it decrements every 10.24µs.
Each time the DMA writes to the done queue it resets the timer to the count placed into it by the host. On
initialization, the host sets a value into the TDQFFT that indicates the maximum time the DMA should
wait in between writes to the done queue. For example, with a PCLK of 33MHz, the range of wait times
is from 7.8µs (RDQFFT = 0001h) to 508ms (RDQFFT = FFFFh). With a PCLK of 25MHz, the wait
times range from 10.2µs (RDQFFT = 0001h) to 671ms (RDQFFT = FFFFh).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15/Transmit Done-Queue FIFO Flush Timer Control Bits (TC0 to TC15). Please note that on system
reset, the timer is set to 0000h, which is defined as an illegal setting. If the receive done-queue FIFO is to be
activated (TDQFE = 1), the host must first configure the timer to a proper state and then set the TDQFE bit
to 1.
0000h = illegal setting
0001h = timer count resets to 1
FFFFh = timer count resets to 65,536
TC15
TC7
15
7
0
0
TDQFFT
Transmit Done-Queue FIFO Flush Timer
0844h
TC14
TC6
14
6
0
0
TC13
TC5
13
5
0
0
123 of 183
TC12
TC4
12
4
0
0
TC11
TC3
11
3
0
0
TC10
TC2
10
2
0
0
TC1
TC9
1
0
9
0
TC0
TC8
0
0
8
0
5