DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 25

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Signal Name:
Signal Description:
Signal Type:
This active-low (open drain) signal is asserted low asynchronously when the device is requesting attention from
the device driver. PINTA is deasserted when the device-interrupting source has been serviced or masked. This
signal is updated on the rising edge of PCLK.
3.6 PCI Extension Signals
These signals are not part of the normal PCI bus signal set. There are additional signals that are asserted when the
DS31256 is an initiator on the PCI bus to help users interpret the normal PCI bus signal set and connect them to a
non-PCI environment like an Intel i960-type bus.
Signal Name:
Signal Description:
Signal Type:
This active-low signal is asserted low on the same clock edge as PFRAME and is deasserted after one clock
period. This signal is only asserted when the device is an initiator. This signal is an output and is updated on the
rising edge of PCLK.
Signal Name:
Signal Description:
Signal Type:
This active-low signal is asserted when the PCI bus either contains valid data to be read from the device or can
accept valid data that is written into the device. This signal is only asserted when the device is an initiator. This
signal is an output and is updated on the rising edge of PCLK.
Signal Name:
Signal Description:
Signal Type:
This active-low signal is asserted on the same clock edge as PFRAME is deasserted and is deasserted on the same
clock edge as PIRDY is deasserted. This signal is only asserted when the device is an initiator. This signal is an
output and is updated on the rising edge of PCLK.
3.7 Supply and Test Signal Description
Signal Name:
Signal Description:
Signal Type:
This input should be left open-circuited by the user.
Signal Name:
Signal Description:
Signal Type:
3.3V (±10%). All V
Signal Name:
Signal Description:
Signal Type:
All V
SS
signals should be connected to the local ground plane.
DD
signals should be connected together.
PINTA
PCI Interrupt
Output (open drain)
PXAS
PCI Extension Address Strobe
Output
PXDS
PCI Extension Data Strobe
Output
PXBLAST
PCI Extension Burst Last
Output
TEST
Factory Test Input
Input (with internal 10kΩ pullup)
V
Positive Supply
n/a
V
Ground Reference
n/a
DD
SS
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