DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 55

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit 15/Receive DS0 Channel Enable (RCHEN). This bit must be set for each active DS0 channel in a
channelized application. In a channelized application, although a DS0 channel is deactivated, the channel can still
be set up to route data to the V.54 detector and/or the BERT block. In addition, although a DS0 channel is active,
the loopback function (CLLB = 1) overrides this activation and routes transmit data back to the HDLC controller
instead of the data coming in through the RD pin. In an unchannelized mode (RUEN = 1), only the RCHEN bit in
R[n]CFG0 needs to be configured.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 7/Transmit Channel Number (TCH#). The CPU loads the number of the HDLC channels associated
with this particular DS0 channel. If the port is running in an unchannelized mode (TUEN = 1), the HDLC channel
number only needs to be loaded into T[n]CFG0. If the fast (52Mbps) HDLC engine is enabled on port 0, HDLC
channel 1 is assigned to it and, likewise, HDLC channel 2 is assigned to the fast HDLC engine on port 2, if it is
enabled. Therefore, these HDLC channel numbers should not be used if the fast HDLC engines are enabled.
Bit 8/Transmit 56kbps (T56). If the port is running a channelized application, this bit determines whether or not
the LSB of each DS0 should be processed. If this bit is set, the LSB of each DS0 channel is not routed from the
HDLC controller (or the BERT, if it has been enabled through the RBERT bit), and the LSB bit position is forced
to 1.
Bit 9/Transmit Force All Ones (TFAO). If this bit is set, then eight 1s are placed into the DS0 channel for
transmission instead of the data that is being sourced from the HDLC controller. If this bit is cleared, the data from
the HDLC controller is transmitted. This bit is useful in instances when CLLB is being activated to keep the
looped back data from being sent out onto the network. This bit overrides TCHEN.
Bit 11/Channelized Network Loopback Enable (CNLB). Enabling this loopback forces the receive data to
replace the transmit data. This bit must be set for each and every DS0 channel that is to be looped back. This bit
overrides TBERT, TFAO, and TCHEN.
0 = deactivated DS0 channel
1 = active DS0 channel
00000000 (00h) = HDLC channel number 1 (also used for the fast HDLC engine on port 0)
00000001 (01h) = HDLC channel number 2 (also used for the fast HDLC engine on port 1)
00000010 (02h) = HDLC channel number 3 (also used for the fast HDLC engine on port 2)
00000011 (03h) = HDLC channel number 4
11111111 (FFh) = HDLC channel number 256
0 = 64kbps (use all 8 bits in the DS0)
1 = 56kbps (use only the first 7 bits transmitted in the DS0; force the LSB to 1)
0 = transmit data from the HDLC controller
1 = force transmit data to all 1s
0 = loopback disabled
1 = loopback enabled
TCHEN
15
7
T[n]CFG[j], where n = 0 to 15 for each port and j = 0 to 127 for each DS0
Transmit Layer 1 Configuration Register
Indirect Access through CP[n]RD
TBERT
14
6
TCH#(8): Transmit HDLC Channel Number
n/a
13
5
55 of 183
n/a
12
4
CNLB
11
3
n/a
10
2
TFAO
1
9
T56
0
8