DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 7

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 1-A. Data Sheet Definitions
The following terms are used throughout this data sheet.
Note: The DS31256’s ports are numbered 0 to 255; the HDLC channels are numbered 1 to 256. HDLC Channel 1 is always associated with
Port 0, HDLC Channel 2 with Port 1, and so on.
2. DETAILED DESCRIPTION
This data sheet is broken into sections detailing each of the DS31256’s blocks. See
diagram.
The Layer 1 block handles the physical input and output of serial data to and from the DS31256. The
DS31256 can handle up to 60 T1 or 64 E1 data streams or two T3 data streams simultaneously. Each of
the 16 physical ports can handle up to two or four T1 or E1 data streams. Section
common applications for the DS31256. The Layer 1 block prepares the incoming data for the HDLC
block and grooms data from the HDLC block for transmission. The block can perform both channelized
and unchannelized loopbacks as well as search for V.54 loop patterns. It is in the Layer 1 block that the
host enables HDLC channels and assigns them to a particular port and/or DS0 channel(s). The host
assigns HDLC channels through the R[n]CFG[j] and T[n]CFG[j] registers, which are described in
Section 6.3. The Layer 1 block interfaces directly to the BERT block. The BERT block can generate and
detect both pseudorandom and repeating bit patterns, and is used to test and stress data communication
links.
The HDLC block consists of two types of HDLC controllers. There are 16 slow HDLC engines (one for
each port) that are capable of operating at speeds up to 8.192Mbps in channelized mode and up to
10Mbps in unchannelized mode. There are also three fast HDLC engines, which only reside on Ports 0,
1, and 2 and they are capable of operating at speeds up to 52Mbps. Via the RP[n]CR and TP[n]CR
registers in the Layer 1 block, the host configures Ports 0, 1, and 2 to use either the slow or the fast
HDLC engine. The HDLC engines perform all of the Layer 2 processing, including zero stuffing and
destuffing, flag generation and detection, CRC generation and checking, abort generation and checking.
In the receive path, the following process occurs. The HDLC engines collect the incoming data into
32-bit dwords and then signal the FIFO that the engine has data to transfer to the FIFO. The 16 ports are
priority decoded (Port 0 gets the highest priority) for the transfer of data from the HDLC Engines to the
FIFO Block. Please note that in a channelized application, a single port may contain up to 128 HDLC
channels and since HDLC channel numbers can be assigned randomly, the HDLC channel number has
no bearing on the priority of this data transfer. This situation is of no real concern however since the
BERT
Descriptor
Dword
DMA
FIFO
HDLC
Host
n/a
V.54
TERM
A pseudorandom pattern that controls loopbacks (see ANSI T1.403)
Bit Error-Rate Tester
A message passed back and forth between the DMA and the host
Double word; a 32-bit data entity
Direct Memory Access
First In, First Out. A temporary memory storage scheme.
High-Level Data-Link Control
The main controller that resides on the PCI Bus.
Not assigned
DEFINITION
7 of 183
Figure 2-1
17
details a few
for a block