DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 79

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
the data that is currently present in the RFHWM register and write it to the channel location indicated by the HCID
bits. When the device has completed the write, the IAB is set to 0.
Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set
to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is
ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the
write operation has completed.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 9/High Watermark (RHWM0 to RHWM9). These bits indicate the setting of the receive high-
watermark. The high-watermark setting is the number of successive blocks that the HDLC controller writes to the
FIFO before the DMA sends the data to the PCI bus. The high-watermark setting must be between (inclusive) one
block and one less than the number of blocks in the link-list chain for the particular channel involved. For
example, if four blocks are linked together, the high watermark can be set to either 1, 2, or 3. In other words, the
high watermark can be set to a value of 1 to N - 1, where N = number of block linked together. Any other numbers
are illegal.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
0000000000 (000h) = invalid setting
0000000001 (001h) = high watermark is 1 block
0000000010 (002h) = high watermark is 2 blocks
0111111111 (1FFh) = high watermark is 511 blocks
1111111111 (3FFh) = high watermark is 1023 blocks
RHWM7
HCID7
IAB
n/a
15
15
7
7
0
0
RFHWM
Receive FIFO High Watermark
0924h
TFSBPIS
Transmit FIFO Starting Block Pointer Indirect Select
0980h
RHWM6
HCID6
IARW
n/a
14
14
6
6
0
0
RHWM5
HCID5
n/a
13
n/a
13
5
0
0
5
HCID4
RHWM4
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n/a
12
4
0
0
n/a
12
4
HCID3
RHWM3
n/a
11
3
0
0
n/a
11
3
HCID2
RHWM2
n/a
10
2
0
0
n/a
10
2
HCID1
n/a
1
0
9
0
RHWM1
RHWM9
1
9
HCID0
n/a
0
8
0
0
RHWM8
RHWM0
0
8