DS31256 Maxim Integrated Products, DS31256 Datasheet
DS31256
Specifications of DS31256
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DS31256 Summary of contents
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... The DS31256 Envoy is a 256-channel HDLC controller that can handle data streams or two T3 data streams. Each of the 16 physical ports can handle one, two, or four data streams. The DS31256 is composed of the following blocks: Layer 1, HDLC processing, FIFO, DMA, PCI bus, and local bus. ...
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MAIN FEATURES............................................................................................................6 2. DETAILED DESCRIPTION ..............................................................................................7 3. SIGNAL DESCRIPTION ................................................................................................13 3 VERVIEW IGNAL 3 ERIAL ORT NTERFACE 3 OCAL US IGNAL 3.4 JTAG S D IGNAL ESCRIPTION 3.5 PCI ...
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DMA Channel Configuration RAM .................................................................................................... 102 9 .......................................................................................................................105 RANSMIT IDE 9.3.1 Overview ........................................................................................................................................... 105 9.3.2 Packet Descriptors ............................................................................................................................ 114 9.3.3 Pending Queue ................................................................................................................................. 116 9.3.4 Done Queue...................................................................................................................................... 120 9.3.5 DMA Configuration RAM................................................................................................................... 125 10. PCI BUS.......................................................................................................................130 10.1 ...
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Figure 2-1. Block Diagram .......................................................................................................................10 Figure 5-1. Status Register Block Diagram for SM and SV54 .................................................................36 Figure 6-1. Layer 1 Block Diagram ..........................................................................................................46 Figure 6-2. Port Timing (Channelized and Unchannelized Applications) ................................................47 Figure 6-3. Layer 1 Register Set .............................................................................................................51 Figure ...
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Figure 11-12. 8-Bit Write Cycle..............................................................................................................162 Figure 12-1. Block Diagram ...................................................................................................................163 Figure 12-2. TAP Controller State Machine...........................................................................................164 Figure 13-1. Layer 1 Port AC Timing Diagram ......................................................................................169 Figure 13-2. Local Bus Bridge Mode (LMS = 0) AC Timing Diagram....................................................170 Figure 13-3. Local ...
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... Small block size of 16 Bytes allows maximum flexibility Programmable low and high watermarks Programmable HDLC channel priority setting Governing Specifications The DS31256 fully meets the following specifications: • ANSI (American National Standards Institute) T1.403-1995 Network-to-Customer Installation DS1 Metallic Interface March 21, 1995 • ...
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... Table 1-A. Data Sheet Definitions The following terms are used throughout this data sheet. Note: The DS31256’s ports are numbered 0 to 255; the HDLC channels are numbered 1 to 256. HDLC Channel 1 is always associated with Port 0, HDLC Channel 2 with Port 1, and so on. ...
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... EOF is reached), the FIFO will begin transferring 32-bit dwords to the HDLC engine. One of the unique attributes of the DS31256 is the structure of the DMA. The DMA has been optimized to maintain maximum flexibility yet reduce the number of bus cycles required to transfer packet data. ...
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... The bridge mode allows the host on the PCI Bus to access the local bus. The DS31256 maps data from the PCI Bus to the local bus. In the configuration mode, the local bus is used only to control and monitor the DS31256 while the HDLC packet data will still be transferred to the host through the PCI Bus ...
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... JTMS Access JTCLK (Sec. 12) JTDO RECEIVE DIRECTION TRANSMIT DIRECTION HDLC FIFO Block Block (Sec. 8) (Sec. 7) BERT ( . Sec 6.5) Dallas Semiconductor DS31256 10 of 183 PCLK PRST PAD[31:0] PCBE[3:0] PPAR PFRAME PIRDY DMA PCI PTRDY Block Block PSTOP PIDSEL (Sec. 10) (Sec. 9) PDEVSEL PREQ ...
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... Restrictions In creating the overall system architecture, the user must balance the port, throughput, and HDLC channel restrictions of the DS31256. Table 2-A. Restrictions ITEM Port Maximum of 16 channelized and unchannelized physical ports Ports Maximum data rate of 52Mbps Unchannelized Ports 3 to 15: Maximum data rate of 10Mbps ...
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Table 2-B. Initialization Steps INITIALIZATION STEP 1) Initialize the PCI configuration registers 2) Initialize all indirect registers 3) Configure the device for operation 4) Enable the HDLC channels 5) Load the DMA descriptors 6) Enable the DMAs 7) Enable DMA ...
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... SIGNAL DESCRIPTION 3.1 Overview/Signal List This section describes the input and output signals on the DS31256. Signal names follow a convention that is shown in the Signal Naming Convention table below. type, description, and pin location. Signal Naming Convention FIRST LETTER SIGNAL CATEGORY R Receive Serial Port ...
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PIN NAME T20 LD4 R18 LD5 P17 LD6 R19 LD7 R20 LD8 P18 LD9 P19 LD10 P20 LD11 N18 LD12 N19 LD13 N20 LD14 M17 LD15 L18 LHLDA (LBG) L19 LHOLD (LBR) M18 LIM K20 LINT M19 LMS LRD (LDS) ...
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PIN NAME W5 PAD27 V5 PAD28 Y4 PAD29 Y3 PAD30 U5 PAD31 Y16 PCBE0 V12 PCBE1 PCBE2 Y9 PCBE3 W6 Y2 PCLK PDEVSEL Y11 PFRAME W10 PGNT W4 Y6 PIDSEL W18 PINT V10 PIRDY W12 PPAR V11 PPERR V4 PREQ ...
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PIN NAME A14 RD10 B12 RD11 C10 RD12 A7 RD13 D7 RD14 A3 RD15 C2 RS0 E3 RS1 F1 RS2 H1 RS3 M2 RS4 P2 RS5 R3 RS6 T4 RS7 C17 RS8 A16 RS9 B14 RS10 C12 RS11 B10 RS12 ...
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PIN NAME A4 TD14 B3 TD15 C3 TEST E4 TS0 F3 TS1 G1 TS2 J2 TS3 N2 TS4 R2 TS5 T3 TS6 W1 TS7 A17 TS8 B15 TS9 B13 TS10 B11 TS11 B9 TS12 A6 TS13 B5 TS14 C4 TS15 ...
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... RC clocks early. This input sync signal resets a counter that rolls over at a count of either 193 (T1 mode) or 256 (E1 mode) or 512 (4.096MHz mode) or 1024 (8.192MHz mode) RC clocks acceptable to pulse the RS signal once to establish byte boundaries and allow the DS31256 to track the byte/frame boundaries by counting RC clocks. If the incoming data does not require alignment to byte/frame boundaries, this signal should be wired low ...
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... TC clocks early. This input sync signal resets a counter that rolls over at a count of either 193 (T1 mode) or 256 (E1 mode) or 512 (4.096MHz mode) or 1024 (8.192MHz mode) TC clocks acceptable to pulse the TS signal once to establish byte boundaries and allow the DS31256 to track the byte/frame boundaries by counting TC clocks. If the incoming data does not require alignment to byte/frame boundaries, this signal should be wired low ...
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Only the 16-bit bus width is allowed (i.e., byte addressing is not available). Signal Name: LA0 to LA19 Signal Description: Local Bus Nonmultiplexed Address Bus Signal Type: Input/Output (tri-state capable) In the PCI ...
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... Signal Type: Output This signal is asserted when the DS31256 is attempting to control the local bus. In Intel mode (LIM = 0), this signal is an active-high signal; in Motorola mode (LIM = 1) this signal is an active-low signal deasserted concurrently with LBGACK. This signal is tri-stated when the local bus is in configuration mode (LMS = 1) and also in PCI bridge mode (LMS = 0) when the local bus arbitration is disabled through the LBBMC register ...
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JTAG Signal Description Signal Name: JTCLK Signal Description: JTAG IEEE 1149.1 Test Serial Clock Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If ...
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They remain outputs for the data phase( write transaction and become inputs for a read transaction. When the device is a target, these signals are always inputs during the ...
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Signal Name: PSTOP Signal Description: PCI Stop Signal Type: Input/Output (tri-state capable) The target creates this active-low signal to signal the initiator to stop the current bus transaction. When the device is a target, this signal is an output and ...
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... These signals are not part of the normal PCI bus signal set. There are additional signals that are asserted when the DS31256 is an initiator on the PCI bus to help users interpret the normal PCI bus signal set and connect them to a non-PCI environment like an Intel i960-type bus. ...
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MEMORY MAP 4.1 Introduction All addresses within the memory map are on dword boundaries, even though all internal device configuration registers are only one word (16 bits) wide. The memory map consumes an address range of 4kB (12 bits). ...
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Receive Port Registers (1xx) OFFSET/ NAME ADDRESS 0100 RP0CR 0104 RP1CR 0108 RP2CR 010C RP3CR 0110 RP4CR 0114 RP5CR 0118 RP6CR 011C RP7CR 0120 RP8CR 0124 RP9CR 0128 RP10CR 012C RP11CR 0130 RP12CR 0134 RP13CR 0138 RP14CR 013C RP15CR ...
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Channelized Port Registers (3xx) OFFSET/ NAME ADDRESS 0300 CP0RDIS 0304 CP0RD 0308 CP1RDIS 030C CP1RD 0310 CP2RDIS 0314 CP2RD 0318 CP3RDIS 031C CP3RD 0320 CP4RDIS 0324 CP4RD 0328 CP5RDIS 032C CP5RD 0330 CP6RDIS 0334 CP6RD 0338 CP7RDIS 033C CP7RD ...
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HDLC Registers (4xx) OFFSET/ NAME ADDRESS 0400 RHCDIS 0404 RHCD 0410 RHPL 0480 THCDIS 0484 THCD 4.7 BERT Registers (5xx) OFFSET/ NAME ADDRESS 0500 BERTC0 0504 BERTC1 0508 BERTRP0 050C BERTRP1 0510 BERTBC0 0514 BERTBC1 0518 BERTEC0 051C BERTEC1 ...
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Transmit DMA Registers (8xx) OFFSET/ NAME ADDRESS 0800 TPQBA0 0804 TPQBA1 0808 TPQEA 080C TPQWP 0810 TPQRP 0830 TDQBA0 0834 TDQBA1 0838 TDQEA 083C TDQRP 0840 TDQWP 0844 TDQFFT 0850 TDBA0 0854 TDBA1 0870 TDMACIS 0874 TDMAC 0880 TDMAQ ...
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PCI Configuration Registers for Function 0 (PIDSEL/Axx) OFFSET/ NAME ADDRESS 0x000/0A00 PVID0 0x004/0A04 PCMD0 0x008/0A08 PRCC0 0x00C/0A0C PLTH0 0x010/0A10 PDCM 0x03C/0A3C PINTL0 4.12 PCI Configuration Registers for Function 1 (PIDSEL/Bxx) OFFSET/ NAME ADDRESS 0x100/0B00 PVID1 0x104/0B04 PCMD1 0x108/0B08 PRCC1 ...
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GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT 5.1 Master Reset and ID Register Description The master reset and ID (MRID) register can be used to globally reset the device. When the RST bit is set to 1, all the internal registers ...
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Bit 0/Receive DMA Enable (RDE). This bit is used to enable the receive DMA. When it is set to 0, the receive DMA does not pass any data from the receive FIFO to the PCI bus, even if one or ...
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Bits 7 to 11/BERT Port Select Bits (BPS0 to BPS4). These bits select which port has the dedicated resources of the BERT. 00000 = Port 0 01000 = Port 8 00001 = Port 1 01001 = Port ...
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COFA (IERC) and interrupt enable for the transmit COFA (IETC) control bits in the RP[n]CR and TP[n]CR registers, respectively. The BERT receiver reports three events: a change in the receive synchronizer status, a bit error ...
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Figure 5-1. Status Register Block Diagram for SM and SV54 BERT BERTEC0 Bit 1 (BECO) BERTEC0 Bit 2 (BBCO) BERTC0 Bit 13 (IEOF) Change in BERTEC0 Bit 0 (SYNC) BERTC0 Bit 15 (IESYNC) BERTEC0 Bit 3 (BED) BERTC0 Bit 14 ...
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Status and Interrupt Register Description Register Name: SM Register Description: Status Master Register Register Address: 0020h Bit # 7 6 Name n/a n/a Default 0 0 Bit # 15 14 Name LBINT LBE Default 0 0 Note: Bits that ...
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Bit 14/Status Bit for Local Bus Error (LBE). This status bit applies to the local bus when it is operated in PCI bridge mode set to 1 when the local bus LRDY signal is not detected within nine ...
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Bit 15/Status Bit for Local Bus Interrupt (LBINT interrupt masked 1 = interrupt unmasked Register Name: SV54 Register Description: Status Register for the Receive V.54 Detector Register Address: 0030h Bit # 7 6 Name SLBP7 SLBP6 Default 0 ...
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Register Name: SDMA Register Description: Status Register for DMA Register Address: 0028h Bit # 7 Name RLBRE RLBR Default 0 Bit # 15 Name TDQWE TDQW Default 0 Note: Bits that are underlined are read-only; all other bits are read-write. ...
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Bit 8/Status Bit for Receive DMA Small Buffer Read (RSBR). This status bit is set to 1 each time the receive DMA completes a single read or a burst read of the small buffer free queue. The RSBR bit is ...
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Register Name: ISDMA Register Description: Interrupt Mask Register for SDMA Register Address: 002Ch Bit # 7 6 Name RLBRE RLBR Default 0 0 Bit # 15 14 Name TDQWE TDQW Default 0 0 Note: Bits that are underlined are read-only; ...
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... Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Factory Test (FT). This bit is used by the factory to place the DS31256 into the test mode. For normal device operation, this bit should be set to 0 whenever this register is written to. Setting this bit places the RAMs into a low-power standby mode ...
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... T1/E1 data stream is applied to the port, the individual T1/E1 data streams must be TDM into a single data stream at either a 4.096MHz or 8.192MHz data rate. Since the DS31256 can map any HDLC channel to any DS0 channel, it can support any form (byte interleaved, frame interleaved, etc.) of TDM that the application may require ...
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... The DS31256 contains an on-board full-featured BERT capable of generating and detecting both pseudorandom and repeating serial bit patterns. The BERT function is a shared resource among the 16 ports on the DS31256 and can only be assigned to one port at a time. It can be used in both channelized and unchannelized applications and at speeds up to 52MHz. In channelized applications, data can be routed to and from any combination of DS0 channels that are being used on the port ...
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Figure 6-1. Layer 1 Block Diagram Local Invert RS Loop- Clock / RD Back Data / (LLB) Sync LLB TC Invert TS Clock / Data / Sync Force TD All Ones BERT/ Fast Ports HDLC 0, ...
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Figure 6-2. Port Timing (Channelized and Unchannelized Applications) RC[n] / TC[n] Normal Mode RC[n] / TC[n] Inverted Mode RD[n] TD[n] RS[n] / TS[n] 0 Clock Early & Not Inverted RS[n] / TS[n] 1/2 Clock Early & Inverted RS[n] / TS[n] ...
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Port Register Descriptions Receive-Side Control Bits (one each for all 16 ports) Register Name: RP[n]CR, where for each port Register Description: Receive Port [n] Control Register Register Address: See the Register Map in Section ...
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Bit 8/Port 0 High-Speed Mode (RP0 (1, 2) HS). If enabled, the port Layer 1 state machine logic is defeated, and RC0 (1, 2) and RD0 (1, 2) are routed to some dedicated high-speed HDLC processing ...
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Bit 0/Invert Clock Enable (TICE not invert clock (normal mode invert clock (inverted mode) Bit 1/Invert Data Enable (TIDE not invert data (normal mode invert data (inverted mode) Bit 2/Invert ...
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Bit 14/Interrupt Enable for TCOFA (IETC interrupt masked 1 = interrupt enabled Bit 15/COFA Status Bit (TCOFA). This latched read-only status bit is set if a COFA is detected. A COFA is detected by sensing that a sync ...
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Register Name: CP[n]RDIS, where for each port Register Description: Channelized Port [n] Register Data Indirect Select Register Address: See the Register Map in Section 4. Bit # 7 6 Name n/a CHID6 Default 0 0 ...
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Register Name: CP[n]RD, where for each port Register Description: Channelized Port [n] Register Data Register Address: See the Register Map in Section 4. Bit # 7 6 Name CHD7 CHD6 Default 0 0 Bit # ...
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Bits 8 to 15/Transmit DS0 Data (TDATA). This register holds the most current DS0 byte transmitted used by the receive-side Layer 1 state machine when channelized local loopback (CLLB) is enabled. Register Name: R[n]CFG[j] where ...
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Bit 15/Receive DS0 Channel Enable (RCHEN). This bit must be set for each active DS0 channel in a channelized application channelized application, although a DS0 channel is deactivated, the channel can still be set up to route data ...
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Bit 14/Route Data from BERT (TBERT). Setting this bit routes DS0 data to the TD pin from the BERT block instead of from the HDLC controller. If the DS0 channel has been configured for 56kbps operation (T56 = 1), the ...
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Table 6-B. Receive V.54 Search Routine STEP DIRECTION 1 Set up the channel search 2 Toggle VRST 3 Wait for SLBP 4 Read VTO and VLB FUNCTION By configuring the RV54 bit in the R[n]CFG[j] register, the host determines in ...
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Figure 6-5. Receive V.54 Host Algorithm Yes ALGORITHM NOTES DS0 channels can be configured to search Set Up the DS0 Channel for the V.54 loop pattern via the Receive Search Layer 1 Configuration Register (Section 6.3) VRST is a control ...
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Figure 6-6. Receive V.54 State Machine Search for Loop Up Pattern for 32 VCLKs Sync = 0 Reset 4 second timer; wait for Loss of Sync or All 1s ( Row) or for the 4 second timer to ...
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BERT The BERT block is capable of generating and detecting the following patterns: The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS A repetitive pattern from bits in length Alternating (16-bit) words that flip every 1 to ...
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BERT Register Description Figure 6-8. BERT Register Set BERTC0: BERT Control 0 n/a TINV MSB IESYNC IEBED BERTC1: BERT Control 1 EIB2 EIB1 MSB BERTRP0: BERT Repetitive Pattern Set 0 (lower word) MSB BERTRP1: BERT Repetitive Pattern Set 1 ...
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Register Name: BERTC0 Register Description: BERT Control Register 0 Register Address: 0500h Bit # 7 Name n/a TINV Default 0 Bit # 15 14 Name IESYNC IEBED Default 0 Note: Bits that are underlined are read-only; all other bits are ...
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Repetitive Pattern Length Map Length Code Length 17 Bits 0000 18 Bits 21 Bits 0100 22 Bits 25 Bits 1000 26 Bits 29 Bits 1100 30 Bits Bit 13/Interrupt Enable for Counter Overflow (IEOF). Allows the receive BERT to cause ...
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EIB2 EIB1 EIB0 Bits 8 to 15/Alternating Word Count Rate. When the BERT is programmed in ...
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Register Name: BERTBC0 Register Description: BERT 32-Bit Bit Counter (lower word) Register Address: 0510h Register Name: BERTBC1 Register Description: BERT 32-Bit Bit Counter (upper word) Register Address: 0514h BERTBC0: BERT Bit Counter 0 (lower word) Bit # 7 6 Name ...
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Bit 1/BERT Error Counter Overflow (BECO). A latched bit that is set when the 24-bit BERT error counter (BEC) overflows. Cleared when read and is not set again until another overflow occurs. Bit 2/BERT Bit Counter Overflow (BBCO). A latched ...
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... The HDLC controllers can handle all required normal real-time tasks. supported by the receive HDLC and Each of the 256 HDLC channels within the DS31256 are configured by the host through the receive HDLC channel definition (RHCD) and transmit channel definition (THCD) registers. There is a separate RHCD and THCD register for each HDLC channel ...
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Table 7-B. Receive HDLC Functions FUNCTION Zero Destuff This operation is disabled if the channel is set to transparent mode. Flag Detection and Okay to have two packets separated by only one flag or by two flags sharing a 0. ...
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HDLC Register Description Register Name: RHCDIS Register Description: Receive HDLC Channel Definition Indirect Select Register Address: 0400h Bit # 7 6 Name HCID7 HCID6 Default 0 0 Bit # 15 14 Name IAB IARW Default 0 0 Note: Bits ...
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FCS checking. When in transparent mode, the device must not be configured to write done-queue descriptors only at the end of a packet desired that done- queue descriptors ...
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Register Name: RHPL Register Description: Receive HDLC Maximum Packet Length Register Address: 0410h Bit # 7 6 Name RHPL7 RHPL6 Default 0 0 Bit # 15 14 Name RHPL15 RHPL14 Default 0 0 Note: Bits that are underlined are read-only; ...
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Register Name: THCD Register Description: Transmit HDLC Channel Definition Register Address: 0484h Bit # 7 6 Name TABTE TCFCS Default Bit # 15 14 Name n/a n/a Default Note: Bits that are underlined are read only, all other bits are ...
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Bits 8 to 11/Transmit Flag Generation Bits (TFG0/TFG1/TFG2/TFG3). These four bits determine how many flags and interfill bytes are sent between consecutive packets. TFG3 TFG2 TFG1 ...
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... FIFO 8.1 General Description and Example The DS31256 contains one 16kB FIFO for the receive path and another 16kB FIFO for the transmit path. Both of these FIFOs are organized into blocks. Since a block is defined as 4 dwords (16 Bytes), each FIFO is made up of 1024 blocks. ...
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Figure 8-1. FIFO Example HDLC Starting Block Channel Pointer Number CH 1 not used CH 2 Block Pointer 125 CH 3 not used CH 4 not used CH 5 not used CH 6 Block Pointer 113 CH 7 not used ...
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Receive High Watermark The high watermark tells the device how many blocks the HDLC engines should write into the receive FIFO before the DMA sends data to the PCI bus, or rather, how full the FIFO should get before ...
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Bit 14/Indirect Access Read/Write (IARW). When the host wishes to write data to set the internal receive starting block pointer, the host should write this bit to 0. This causes the device to take data that is currently presetn in ...
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... Note: The RFSBP is write-only memory. Once this register has been written to and the operation has started, the DS31256 internal state machine changes the value in this memory. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1 ...
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RFHWM register and write it to the channel location indicated by the HCID bits. When the device has completed the write, the IAB is set to 0. Bit 15/Indirect Access Busy (IAB). ...
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... Note: The TFSBP register is write-only memory. Once this register has been written to and the operation has started, the DS31256 internal state machine changes the value in this memory. Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set to 1 ...
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Bits 0 to 9/Block ID (BLKID0 to BLKID9) 00000000000 (000h) = block number 0 01111111111 (1FFh) = block number 511 1111111111 (3FFh) = block number 1023 Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the ...
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Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal transmit low- watermark RAM, this bit should be written the host. This causes the device to begin obtaining the data from the ...
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... DMA can be used directly by the transmit DMA. The receive and transmit portions of the DMA are completely independent and are discussed separately. The DS31256 has no restrictions on the transmit side, but has the following restrictions on the location and size of receive buffers in host memory: • ...
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Table 9-A. DMA Registers to be Configured by the Host on Power-Up ADDRESS NAME 0700 RFQBA0 0704 RFQBA1 0708 RFQEA 070C RFQSBSA 0710 RFQLBWP 0714 RFQSBWP 0718 RFQLBRP 071C RFQSBRP 0730 RDQBA0 0734 RDQBA1 0738 RDQEA 073C RDQRP 0740 RDQWP ...
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Receive Side 9.2.1 Overview The receive DMA uses a scatter-gather technique to write packet data into main memory. The host keeps track of and decides where the DMA should place the incoming packet data. There are a set of ...
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On an HDLC-channel basis in the receive DMA configuration RAM, the host instructs the DMA how to use the large and small buffers for the incoming packet data on that particular HDLC channel. The host has three options: (1) only ...
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Host Actions The host typically handles the receive DMA as follows: 1) The host is always trying to make free data buffer space available and therefore tries to fill the free- queue descriptor. 2) The host either polls ...
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Figure 9-1. Receive DMA Operation Free Queue Descriptors (circular queue) Free Data Buffer Address 00h unused Free Desc. Ptr. Free Data Buffer Address 08h unused Free Desc. Ptr. Free Data Buffer Address 10h unused Free Desc. Ptr. Done Queue Descriptors ...
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Figure 9-2. Receive DMA Memory Organization Internal Registers Free-Queue Base Address (32) Free-Queue Large Buffer Host Write Pointer (16) Free-Queue Large Buffer DMA Read Pointer (16) Free-Queue Small Buffer Start Address (16) Free-Queue Small Buffer Host Write Pointer (16) Free-Queue ...
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Packet Descriptors A contiguous section 65,536 quad dwords that make up the receive packet descriptors resides in main memory. The receive packet descriptors are aligned on a quad dword basis and can be placed anywhere in ...
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... DMA and, in store and forward applications, the receive and transmit packet descriptors have been designed to eliminate the need for the host to groom the descriptors before transmission. In these type of applications, the host should not use dword 3 of the receive packet descriptor. DS31256 256-Channel, High-Throughput HDLC Controller Data Buffer Address (32) Next Descriptor Pointer (16) ...
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... These are accessed by the host and the DMA. On initialization, the host configures all the registers shown in the read pointers and the host only writes to the write pointers. DS31256 256-Channel, High-Throughput HDLC Controller Free Data Buffer Address (32) Free Packet Descriptor Pointer (16) Table 9-E ...
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Empty Case The receive free queue is considered empty when the read and write pointers are identical. Receive Free-Queue Empty State empty descriptor empty descriptor empty descriptor read pointer > empty descriptor empty descriptor empty descriptor empty descriptor Full Case ...
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Figure 9-6. Receive Free-Queue Structure Free-Queue Large Buffer Host Write Pointer Free-Queue Large Buffer DMA Read Pointer Free-Queue Small Buffer Start Address Free-Queue Small Buffer Host Write Pointer Free-Queue Small Buffer DMA Read Pointer Maximum of 65,536 Free-Queue Descriptors Once ...
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Status/Interrupts On each read of the free queue by the DMA, the DMA sets either the status bit for receive DMA large buffer read (RLBR) or the status bit for receive DMA small buffer read (RSBR) in the status register ...
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Register Name: RDMAQ Register Description: Receive DMA Queues Control Register Address: 0780h Bit # 7 6 Name n/a n/a Default 0 0 Bit # 15 14 Name n/a n/a Default 0 0 Note: Bits that are underlined are read-only; all ...
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Done Queue The DMA writes to the receive done queue when it has filled a free data buffer with packet data and has loaded the associated packet descriptor with all the necessary information. The descriptor location is indicated through ...
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The host reads from the receive done queue to find which data buffers and their associated descriptors are ready for processing. The receive done queue is circular. A set of internal addresses within the device that are accessed by the ...
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Figure 9-8. Receive Done-Queue Structure Done-Queue DMA Write Pointer Done-Queue Host Read Pointer Maximum of 65,536 Done-Queue Descriptors Once the receive DMA is activated (through the RDE control bit in the master configuration register, see Section 5), it can begin ...
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The DMA always writes to the done queue when it has finished receiving a packet, even if the threshold has not been met. Done-Queue Burst Writing ...
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Register Name: RDQFFT Register Description: Receive Done-Queue FIFO Flush Timer Register Address: 0744h Bit # 7 6 Name TC7 TC6 Default 0 0 Bit # 15 14 Name TC15 TC14 Default 0 0 Note: Bits that are underlined are read-only, ...
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Bits 8 to 10/Receive Done-Queue Status-Bit Threshold Setting (RDQT0 to RDQT2). These bits determine when the DMA sets the receive DMA done-queue write (RDQW) status bit in the status register for DMA (SDMA) register. 000 = set the RDQW status ...
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FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 0; Bits 0 to 31/Current Data Buffer Address. The current 32-bit address of the data buffer that is being used. This address is used by the DMA to ...
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FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 2; Bits 16 to 28/Byte Count. The DMA uses these 13 bits to keep track of the number of bytes stored in the data buffer. Maximum is 8188 ...
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During a write operation, this bit is set to 1 while the write is taking place set to 0 once the write operation has completed. Register Name: RDMAC Register Description: Receive DMA Channel Configuration ...
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Table 9-G. Transmit DMA Main Operational Areas DESCRIPTORS A dedicated area of memory that describes the location and attributes of the Packet packet data. A dedicated area of memory that the host writes to inform the DMA that Pending Queue ...
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Priority Packets The host has the option to change the order in which packets are transmitted by the DMA. If the host sets the priority packet (PRI) bit in the pending-queue descriptor to 1, the transmit DMA knows that this ...
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Figure 9-10. Transmit DMA Operation Done-Queue Descriptors (circular queue) 00h Status CH#5 Free Desc. Ptr. 04h Status CH#1 Free Desc. Ptr. 08h Status CH# Free Desc. Ptr. 0Ch Status CH# Free Desc. Ptr. 10h Status CH# Free Desc. Ptr. 14h ...
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Figure 9-11. Transmit DMA Memory Organization Internal Registers Pending-Queue Base Address (32) Pending-Queue Host Write Pointer (16) Pending-Queue DMA Read Pointer (16) Pending-Queue End Address (16) Done-Queue Base Address (32) Done-Queue DMA Write Pointer (16) Done-Queue Host Read Pointer (16) ...
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Figure 9-12. Transmit DMA Packet Handling Transmit DMA Configuration RAM Last Pending Descriptor Pointer Next Pending Descriptor Pointer Next Descriptor Pointer Start Descriptor Pointer 1st Descriptor (EOF=0/CV=0) Buffer 1 Packet 1 2nd Descriptor (EOF=0/CV=0) Buffer 2 Packet 1 Last Descriptor ...
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Figure 9-13. Transmit DMA Priority Packet Handling Standard Queue Pointers Last Pending Descriptor Pointer Next Pending Descriptor Pointer Next Descriptor Pointer Start Descriptor Pointer 1st Descriptor (EOF=0/CV=0) 2nd Descriptor (EOF=0/CV=0) Last Descriptor (EOF=1/CV=1) Service Priority Packets Normal Path if No ...
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DMA Updates to the Done Queue The host has two options for when the transmit DMA should write descriptors that have completed transmission to the done queue channel-by-channel basis, through the done-queue select (DQS) bit in the transmit ...
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PV fields in the packet descriptor ready them for transmission). The second option allows the software a cleaner error-recovery technique. See Figure 9-14. Transmit DMA Error Recovery Algorithm Host Actions The host typically handles ...
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Packet Descriptors A contiguous section 65,536 quad dwords that make up the transmit packet descriptors resides in main memory. The transmit packet descriptors are aligned on a quad-dword basis and can be placed anywhere in the ...
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... This field is written to by the transmit DMA to link descriptors together and should always be set the host. dword 3; Bits 17 to 31/Unused. These bits are ignored by the transmit DMA and can be set to any value. DS31256 256-Channel, High-Throughput HDLC Controller Data Buffer Address (32) ...
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... DMA. This field is used by the transmit DMA when it writes to the done queue to inform the host of the status of the outgoing packet data. dword 0; Bits 29 to 31/Unused. Not used by the DMA. Can be set to any value by the host and is ignored by the transmit DMA. DS31256 256-Channel, High-Throughput HDLC Controller CHRST PRI HDLC Channel (8) ...
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The transmit DMA reads from the transmit pending-queue descriptor circular queue which data buffers and their associated descriptors are ready for transmission. A set of internal addresses within the device that are accessed by both the host and the DMA ...
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Figure 9-18. Transmit Pending-Queue Structure Pending-Queue Host Write Pointer Pending-Queue DMA Read Pointer Maximum of 65,536 Pending-Queue Descriptors Once the transmit DMA is activated (by setting the TDE control bit in the master configuration register; see Section 5), it can ...
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DMA pending-queue read (TPQR) in the status register for DMA (SDMA). See Section Register Name: TDMAQ Register Description: Transmit DMA Queues Control Register Address: 0880h Bit # 7 6 Name n/a ...
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... PCI error 111 = transmit FIFO error; it has underflowed dword 0; Bits 29 to 31/Unused. Not used by the DMA. Could be any value when read. DS31256 256-Channel, High-Throughput HDLC Controller PRI HDLC Channel (8) 120 of 183 ...
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The host reads from the transmit done queue to find which data buffers and their associated descriptors have completed transmission. The transmit done queue is circular queue. A set of internal addresses within the device that are accessed by both ...
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Figure 9-20. Transmit Done-Queue Structure Done Queue DMA Write Pointer Done Queue Host Read Pointer Maximum of 65536 Done Queue Descriptors dmatdq Once the transmit DMA is activated (through the TDE control bit in the master configuration register; see Section ...
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When enabled through the transmit done-queue FIFO-enable (TDQFE) bit, the done-queue FIFO does not write to the done queue until it reaches the high watermark. When the done-queue FIFO reaches the high watermark (which is six descriptors), it attempts to ...
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Register Name: TDMAQ Register Description: Transmit DMA Queues Control Register Address: 0880h Bit # 7 Name n/a n/a Default 0 Bit # 15 14 Name n/a n/a Default 0 Note: Bits that are underlined are read-only; all other bits are ...
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DMA Configuration RAM The device contains an on-board set of 1536 dwords (6 dwords per channel times 256 channels) that are used by the host to configure the DMA and used by the DMA to store values locally when ...
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FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 0; Bits 0 to 31/Current Data Buffer Address. This is the current 32-bit address of the data buffer that is being used. This address is used by the ...
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FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 1; Bits 20 to 21/Priority State (PRIST). This field is used by the transmit DMA to keep track of queued priority descriptors as they arrive from the pending ...
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FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD - dword 5; Bits 16 to 31/Next Priority Pending Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base address of the first transmit priority packet descriptor ...
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Register Name: TDMAC Register Description: Transmit DMA Configuration Register Address: 0874h Bit # 7 6 Name D7 D6 Default 0 0 Bit # 15 14 Name D15 D14 Default 0 0 Note: Bits that are underlined are read only, all ...
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... Revision 2.1 (June 1, 1995) of the PCI Local Bus Specification. HDLC packet data always passes to and from the DS31256 through the PCI bus. The user has the option to configure and monitor the internal device registers either through the PCI bus (local bus bridge mode) or through the local bus (local bus configuration mode) ...
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PCI Read Cycle A read cycle on the PCI bus is shown in PFRAME signal and drives the address onto the PAD signal lines and the bus command (which would be a read) onto the PCBE signal lines. The ...
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PCI Write Cycle A write cycle on the PCI bus is shown in PFRAME signal and drives the address onto the PAD signal lines and the bus command (which would be a write) onto the PCBE signal lines. The ...
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PCI Bus Arbitration The PCI bus can be arbitrated as shown in PREQ. A central arbiter grants the access some time later by asserting PGNT. Once the bus has been granted, the initiator waits until both PIRDY and PFRAME ...
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... PSTOP is asserted, data may or may not be transferred. The target always deasserts PSTOP when it detects that the initiator has deasserted PFRAME. When the DS31256 is a target, it disconnects with data after the first data phase is complete, if the master attempts a burst transaction ...
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... If such a scenario occurs, it reports through the target-abort-initiated status bit in the PCI command/status configuration register (Section 10.2). See Section bus operation. When the DS31256 is a bus master detects a target abort, it reports through the target abort detected by master status bit in the PCI command/status configuration register (Section 10.2). ...
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... Figure 10-9 shows an example of a fast back-to-back transaction where no idle cycle exists bus master, the DS31256 cannot perform a Type 2 access target, it can accept both types of fast back- to-back transactions. Figure 10-9. PCI Fast Back-To-Back ...
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... Bits 0 to 15/Vendor ID. These read-only bits identify Dallas Semiconductor as the device’s manufacturer. The vendor ID was assigned by the PCI Special Interest Group and is fixed at 13EAh. Bits 16 to 31/Device ID. These read-only bits identify the DS31256 as the device being used. The device ID was assigned by Dallas Semiconductor and is fixed at 3134h. ...
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Command Bits (PCMD0) Bit 0/I/O Space Control (IOC). This read-only bit is forced the device to indicate that it does not respond to I/O space accesses. Bit 1/Memory Space Control (MSC). This read/write bit controls whether ...
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Status Bits (PCMD0) The upper word in the PCMD0 register is the status portion, which reports events as they occur. As previously mentioned, reads of the status portion occur normally but writes are unique in that bits can only ...
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... PRST pin. Bits 16 to 23/Header Type. These read-only bits are forced to 80h, which indicate a multifunction device. Bits 24 to 31/Built-In Self-Test (BIST). These read only bits are forced to 0. DS31256 256-Channel, High-Throughput HDLC Controller Revision ID (Read Only/Set to 00h) Class Code (Read Only/Set to 00h) ...
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Register Name: PDCM Register Description: PCI Device Configuration Memory Base Address Register Register Address: 0x010h Base Address (Read Only/Set to 0h) Base Address MSB Note: Read-only bits in the PDCM register are underlined; all other bits are read-write. Bit 0/Memory ...
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... Bits 0 to 15/Vendor ID. These read-only bits identify Dallas Semiconductor as the device’s manufacturer. The vendor ID was assigned by the PCI Special Interest Group and is fixed at 13EAh. Bits 16 to 31/Device ID. These read-only bits identify the DS31256 as the device being used. The device ID was assigned by Dallas Semiconductor and is fixed at 3134h. ...
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Command Bits (PCMD1) Bit 0/I/O Space Control (IOC). This read-only bit is forced the device to indicate that it does not respond to I/O space accesses. Bit 1/Memory Space Control (MSC). This read/write bit controls whether ...
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Status Bits (PCMD1) The upper word in the PCMD1 register is the status portion, which reports events as they occur. As mentioned earlier, reads of the status portion occur normally, but writes are unique in that bits can only ...
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Register Name: PRCC1 Register Description: PCI Revision ID/Class Code Register 1 Register Address: 0x108h MSB Bits 0 to 7/Revision ID. These read-only bits identify the specific device revision, selected by Dallas Semiconductor. Bits 8 to 15/Class Code Interface. These read-only ...
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Register Name: PLBM Register Description: PCI Local Bus Memory Base Address Register Register Address: 0x110h Base Address (Read Only/Set to 0h) Base Address MSB Note: Read-only bits in the PLBM register are underlined; all other bits are read-write. Bit 0/Memory ...
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... Figure 11-3 CPU on the local bus configures and monitors the DS31256. In this mode, the host on the PCI/custom bus cannot access the DS31256 and the PCI/custom bus is only used to transfer HDLC packet data to and from the host. Table 11-A lists all the local bus pins and their applications in both operating modes. The local bus operates only in a nonmultiplexed fashion ...
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... Figure 11-2. Bridge Mode with Arbitration Enabled Framer or Transceiver Framer or Transceiver Framer or Transceiver Framer or Transceiver Custom DS31256 Local Bus DS31256 Local Bus Local CPU that Handles the Real-Time Tasks Required by the Interfaces 148 of 183 PCI / Host Bus Processor and Main Memory PCI / ...
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... PCI block returns a target abort to the host. See Section 10 for details about a target abort. DS31256 PCI / Custom Bus No Access Allowed Only Used to Transfer HDLC Data Local Bus CPU Configures and Local RAM & Monitors Ds31256 149 of 183 Host Processor and Main Memory ROM ...
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Table 11-B. Local Bus 8-Bit Width Address, LBHE Setting PCBE [3:0] 1110 1101 1011 0111 Note 1: All other possible states for PCBE cause the device to return a target abort to the host. Note 2: The 8-bit data picked ...
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... It is also used to configure the PCI configuration registers and therefore the PCI bus signal PIDSEL is disabled when the local bus is in the configuration mode. The DS31256 PCI configuration registers can't be accessed via the PCI bus when the DS31256 is in Configuration mode (LMS=1). In this mode no device registers are accessible via the PCI bus. ...
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Figure 11-4. Local Bus Access Flowchart Start 9 Clock Timer LRDY Active? No Timer Expired? No Local Bus Access Progresses Set the LBE Status Bit PCI Host Initiates a Local Bus Access No Is Arbitration Enabled for the Local Bus? ...
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Local Bus Bridge Mode Control Register Description Register Name: LBBMC Register Description: Local Bus Bridge Mode Control Register Address: 0040h Note: This register can only be accessed through the PCI bus and therefore only in the PCI bridge mode. ...
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Bit 6/Local Bus Width (LBW bits bits Bits 8 to 11/Local Bus Arbitration Timer Setting (LAT0 to LAT3). These four bits determine the total time the local bus seizes the bus when it has ...
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Examples of Bus Timing for Local Bus PCI Bridge Mode Operation Figure 11-5. 8-Bit Read Cycle Intel Mode (LIM = 0) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 4 LCLK (LRDY = 0100) An attempted access by ...
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Figure 11-6. 16-Bit Write Cycle Intel Mode (LIM = 0) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 4 LCLK (LRDY = 0100) An attempted access by the host causes the local bus to request the bus. If bus ...
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Figure 11-7. 8-Bit Read Cycle Intel Mode (LIM = 0) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) 1 LCLK LA[19:0] LD[7:0] LD[15:8] LBHE LWR LRD LRDY Note: The LRDY signal must be ...
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Figure 11-8. 16-Bit Write (Only Upper 8 Bits Active) Cycle Intel Mode (LIM = 0) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK 1 LA[19:0] LD[7:0] LD[15:8] LBHE LRD LWR LRDY Note: ...
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Figure 11-9. 8-Bit Read Cycle Motorola Mode (LIM = 1) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 6 LCLK (LRDY = 0110) An attempted access by the host causes the local bus to request the bus. If bus ...
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Figure 11-10. 8-Bit Write Cycle Motorola Mode (LIM = 1) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 6 LCLK (LRDY = 0110) An attempted access by the host causes the local bus to request the bus. If bus ...
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... Bus Transaction Time = Timed from LRDY (LRDY = 0000) LCLK 1 2 LA[19:0] LD[7:0] LD[15:8] LBHE LR/W LDS LRDY Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status bit is set DS31256 256-Channel, High-Throughput HDLC Controller Address Valid 161 of 183 ...
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Figure 11-12. 8-Bit Write Cycle Motorola Mode (LIM = 1) Arbitration Disabled (LARBE = 0) Bus Transaction Time = Timed from LRDY (LRDY = 0000) 1 LCLK LA[19:0] LD[7:0] LD[15:8] LBHE LR/W LDS LRDY Note: The LRDY signal must be ...
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... The DS31256 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. diagram. The DS31256 contains the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture: ...
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TAP Controller State Machine Description This section details the operation of the TAP controller state machine. See each of the states. The TAP controller is a finite state machine, which responds to the logic level at JTMS on the ...
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... Test-Logic-Reset. The TAP controller is in the Test-Logic-Reset state upon DS31256 power-up. The instruction register contains the IDCODE instruction. All system logic on the DS31256 operates normally. Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The instruction and test registers remain idle. ...
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... IDCODE SAMPLE/PRELOAD. SAMPLE/PRELOAD is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the DS31256 can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture- DR state. SAMPLE/PRELOAD also allows the DS31256 to shift data into the boundary scan register through JTDI using the Shift-DR state ...
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... The device ID code always has 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. The device ID code for the DS31256 is 00006143h. 12.4 Test Registers IEEE 1149.1 requires a minimum of two test registers— ...
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... Note 7: The typical values listed above are not production tested. Note 8: Dallas Semiconductor Communications devices are tested in accordance with ESDA STM 5.1-1998. DS31256 256-Channel, High-Throughput HDLC Controller (except V )…………………………………………….-0.3V to +5.5V ...
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... Edge Data Valid on TD Note 9: Ports applications running up to 10MHz. Note 10: Port running in applications up to 52MHz. Note 11: Aggregate, maximum bandwidth and port speed for the DS31256 are directly proportional to PCLK frequency. Throughput measurements are made at PCLK = 33MHz. Figure 13-1. Layer 1 Port AC Timing Diagram ...
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AC CHARACTERISTICS: LOCAL BUS IN BRIDGE MODE (LMS = 3.0V to 3.6V 0°C to +70°C PARAMETER Delay Time from the Rising Edge of PCLK to Output Valid from Tri-state Delay Time from the ...
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AC CHARACTERISTICS: LOCAL BUS IN CONFIGURATION MODE (LMS = 3.0V to 3.6V 0°C to +70°C PARAMETER Setup Time for LA[15:0] Valid to LCS Active Setup Time for LCS Active to Either LRD, LWR, ...
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Figure 13-3. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams Intel Read Cycle LA[15:0] LD[15:0] LWR LCS LRD Intel Write Cycle LA[15:0] LD[15:0] LRD LCS LWR Address Valid Address Valid 172 of ...
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Figure 13-4. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams (continued) Motorola Read Cycle LA[15:0] LD[15:0] LR/W LCS LDS Motorola Write Cycle LA[15:0] LD[15:0] LR/W LCS LDS Address Valid Address Valid 173 ...
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... Active from Tri-State on All PCI Outputs and I/O Note 15: Aggregate, maximum bandwidth and port speed for the DS31256 are directly proportional to PCLK frequency. Ensure that PCLK is 33MHz for maximum throughput. Note 16: The PCI extension signals PABLAST, PXAS, and PXDS have a 15ns max. These signals are not part of the PCI Specification. ...
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AC CHARACTERISTICS: JTAG TEST PORT INTERFACE (V = 3.0V to 3.6V 0°C to +70°C PARAMETER JTCLK Clock Period JTCLK Clock Low Time JTCLK Clock High Time JTMS/JTDI Setup Time to the Rising Edge of JTCLK JTMS/JTDI ...
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... Page 151: Section 11.1.2 Configuration Mode. Added info about how data cannot be passed from the local bus to the PCI bus in this mode—The DS31256 PCI configuration registers cannot be accessed via the PCI bus when the DS31256 is in Configuration mode (LMS=1). In this mode no device registers are accessible via the PCI bus. ...
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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 15.1 256-pin PBGA (27mm x 27mm) (56-G6004-001) ...
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THERMAL CHARACTERISTICS Table 16-A. Thermal Properties, Natural Convection PARAMETER Ambient Temperature Junction Temperature Theta-JA (θ ), Still Air JA Psi-JB (Ψ ), Still Air JB Psi-JT (Ψ ), Still Air JT Note 1: The package is mounted on a ...
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... The T1 and E1 channelized application examples in this section are one of two types. The first type is where a single data stream is routed to and from the DS31256. This is represented as a thin arrow in the application examples second type is where four data streams have been TDM into a single 8.192MHz data stream, which is routed to and from the DS31256 ...
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... Port with 256 HDLC Channel Support Figure 17-4 shows an application where links are framed and interfaced to a single DS31256. The T1 lines can be either clear-channel or channelized. The DS21Q55 quad T1/E1/J1 single-chip transceiver performs the line interface function and frames to the T1/E1/J1 line. ...
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... DS21FT42 12-channel T1 framer devices. The T1 framers locate the frame and multiframe boundaries and interface to the DS31256 by aggregating four T1 lines into a single 8.192MHz data stream, which then flows into and out of the DS31256. The T1 lines can be either clear channel or channelized. Figure 17-5. Dual T3 Application ...
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... DS31256 has enough physical ports to support the application, but aggregation could be done to cut down on the number of electrical connections between the DS31256 and the T1 framers. The T1 lines can be either clear channel or channelized. Figure 17-6. T3 Application (512 HDLC Channels) ...
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... T3 line is demultiplexed by the M13 block and passed to the DS21FF42 and DS21FT42 devices. The T1 framers locate the frame and multiframe boundaries and interface to the DS31256. Aggregating four T1 lines into a single 8.192MHz data stream is not required since the DS31256 has enough physical ports to support the applicationm, but aggregation could be done to cut down on the number of electrical connections between the DS31256 and the T1 framers ...