DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 124

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Transmit Pending-Queue FIFO Enable (TPQFE). See Section
Bit 1/Transmit Pending-Queue FIFO Flush (TPQLF). See Section
Bit 3/Transmit Done-Queue FIFO Enable (TDQFE). This bit must be set to 1 to enable the DMA to burst write
descriptors to the done queue. If this bit is set to 0, descriptors are written one at a time.
Bit 4/Transmit Done-Queue FIFO Flush (TDQF). When this bit is set to 1, the internal done-queue FIFO is
flushed by sending all data into the done queue. This bit must be set to 0 for proper operation.
Bits 8 to 10/Transmit Done-Queue Status Bit Threshold Setting (TDQT0 to TDQT2). These bits determine
when the DMA sets the transmit DMA done-queue write (TDQW) status bit in the status register for DMA
(SDMA) register.
0 = done-queue burst write disabled
1 = done-queue burst write enabled
0 = FIFO in normal operation
1 = FIFO is flushed
000 = set the TDQW status bit after each descriptor write to the done queue
001 = set the TDQW status bit after 2 or more descriptors are written to the done queue
010 = set the TDQW status bit after 4 or more descriptors are written to the done queue
011 = set the TDQW status bit after 8 or more descriptors are written to the done queue
100 = set the TDQW status bit after 16 or more descriptors are written to the done queue
101 = set the TDQW status bit after 32 or more descriptors are written to the done queue
110 = set the TDQW status bit after 64 or more descriptors are written to the done queue
111 = set the TDQW status bit after 128 or more descriptors are written to the done queue
n/a
n/a
15
7
0
0
TDMAQ
Transmit DMA Queues Control
0880h
n/a
n/a
14
6
0
0
n/a
n/a
13
5
0
0
124 of 183
n/a
n/a
12
4
0
0
TDQF
n/a
11
9.3.3
3
0
0
9.3.3
for details.
for details.
TDQFE
TDQT2
10
2
0
0
TDQT1
TPQF
1
0
9
0
TDQT0
TPQFE
0
0
8
0