DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 94

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 9-6. Receive Free-Queue Structure
Once the receive DMA is activated (by setting the RDE control bit in the master configuration register,
see Section 5), it can begin reading data out of the free queue. It knows where to read data out of the free
queue by reading the read pointer and adding it to the base address to obtain the actual 32-bit address.
Once the DMA has read the free queue, it increments the read pointer by two dwords. A check must be
made to ensure the incremented address does not equal or exceed either the receive free-queue small-
buffer start address (in the case of the large buffer circular queue) or the receive free-queue end address
(in the case of the small buffer circular queue). If the incremented address does equal or exceed either of
these addresses, the incremented read pointer is set equal to 0000h.
Maximum of 65,536
Free-Queue Descriptors
Free-Queue Large Buffer
Host Write Pointer
Free-Queue Large Buffer
DMA Read Pointer
Free-Queue Small Buffer
Start Address
Free-Queue Small Buffer
Host Write Pointer
Free-Queue Small Buffer
DMA Read Pointer
Base + End Address
Base + 00h
Base + 08h
Base + 10h
Base + 18h
Base + 20h
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Free-Queue Descriptor
Free-Queue Descriptor
Free-Queue Descriptor
Free-Queue Descriptor
Free-Queue Descriptor
Free-Queue Descriptor
Free-Queue Descriptor
Free Queue Descriptor
Free-Queue Descriptor
Free-Queue Descriptor
Free-Queue Descriptor
Free-Queue Descriptor
Free-Queue Descriptor
DMA Acquired
Host Readied
DMA Acquired
DMA Acquired
DMA Acquired
DMA Acquired
DMA Acquired
Host Readied
Host Readied
Host Readied
Host Readied
Host Readied
Host Readied
Large
Buffer
Circular
Queue
Small
Buffer
Circular
Queue