DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 127

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 1; Bits 20 to 21/Priority State (PRIST). This field is used by the transmit DMA to keep track of queued
priority descriptors as they arrive from the pending queue, and for the DMA to know when it should create a
horizontal linked list of transmit priority descriptors and where it can find the next valid priority descriptor. This
field handles priority packets and the PENDST field handles standard packets.
-FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 1; Bit 22/Processing Priority Packet (PPP). This bit is set to 1 when the DMA is currently processing a
priority packet.
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 1; Bits 23 to 31/Unused. This field is not used by the DMA and could be any value when read.
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 2; Bits 0 to 15/Next Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base
address of the next transmit packet descriptor for the packet that is currently being transmitted. Only valid if
EOF = 0 or if EOF = 1 and CV = 1.
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 2; Bits 16 to 31/Start Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base
address of the first transmit packet descriptor for the packet that is currently being transmitted. If DQS = 0, then
this pointer is written back to the done queue when the packet has completed transmission. This field is used by
the DMA for processing standard as well as priority packets.
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 3; Bits 0 to 15/Next Pending Descriptor Pointer. This 16-bit value is the offset from the transmit
descriptor base address of the first transmit packet descriptor for the packet that is queued up next for
transmission.
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 3; Bits 16 to 31/Last Pending Descriptor Pointer. This 16-bit value is the offset from the transmit
descriptor base address of the first transmit packet descriptor for the packet that is queued up last for transmission.
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 4; Bits 0 to 15/Next Priority Descriptor Pointer. This 16-bit value is the offset from the transmit
descriptor base address of the next transmit priority packet descriptor for the priority packet that is currently being
transmitted. Only valid if EOF = 0 or if EOF = 1 and CV = 1.
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 4; Bits 16 to 31/Unused. This field is not used by the DMA and could be any value when read.
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 5; Bits 0 to 15/Last Priority Pending Descriptor Pointer. This 16-bit value is the offset from the
transmit descriptor base address of the first transmit priority packet descriptor for the priority packet that is queued
up last for transmission.
State
00
01
10
11
Next Priority Descriptor Pointer Field
Not Valid
Not Valid
Valid
Valid
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Next Priority Pending Descriptor Pointer Field
Not Valid
Not Valid
Valid
Valid