DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 60
DS31256
Manufacturer Part Number
DS31256
Description
IC CTRLR HDLC 256-CHANNEL 256BGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS31256.pdf
(183 pages)
Specifications of DS31256
Controller Type
HDLC Controller
Interface
Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
500mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS31256
Manufacturer:
DALLAS
Quantity:
20 000
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6.5 BERT
The BERT block is capable of generating and detecting the following patterns:
The BERT receiver has a 32-bit bit counter and a 24-bit error counter. It can generate interrupts upon
detecting a bit error, a change in synchronization, or if an overflow occurs in the bit and error counters.
See Section
the host must configure the BERT mux
configure the Layer 1 state machine to send/obtain data to/from the BERT block through the Layer 1
configuration registers (Section 6.3).
Figure 6-7. BERT Mux Diagram
The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS
A repetitive pattern from 1 to 32 bits in length
Alternating (16-bit) words that flip every 1 to 256 words
SBERT STATUS
BIT IN SM
5
for details on status bits and interrupts from the BERT block. To activate the BERT block,
INTERNAL CONTROL AND
CONFIGURATION BUS
BLOCK
BERT
(Figure
60 of 183
6-7). In channelized applications, the host must also
BERT SELECT (5)
IN THE MASTER CONFIGURATION REGISTER
BERT
Mux
Port 0 (slow)
Port 1 (slow)
Port 2 (slow)
Port 3 (slow)
Port 4 (slow)
Port 5 (slow)
Port 13 (slow)
Port 14 (slow)
Port 15 (slow)
Port 0 (fast)
Port 1 (fast)
Port 2 (fast)
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