DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 18

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.2 Serial Port Interface Signal Description
Signal Name:
Signal Description:
Signal Type:
Data can be clocked into the device either on rising edges (normal clock mode) or falling edges (inverted clock
mode) of RC. This is programmable on a per port basis. RC0–RC2 can operate at speeds up to 52MHz.
RC3–RC15 can operate at speeds up to 10MHz. Unused signals should be wired low.
Signal Name:
Signal Description:
Signal Type:
Can be sampled either on the rising edge of RC (normal clock mode) or the falling edge of RC (inverted clock
mode). Unused signals should be wired low.
Signal Name:
Signal Description:
Signal Type:
This is a one-RC clock-wide synchronization pulse that can be applied to the DS31256 to force byte/frame
alignment. The applied sync-signal pulse can be either active high (normal sync mode) or active low (inverted
sync mode). The RS signal can be sampled either on the falling edge or on rising edge of RC
applied sync pulse can be during the first RC clock period of a 193/256/512/1024-bit frame or it can be applied
1/2, 1, or 2 RC clocks early. This input sync signal resets a counter that rolls over at a count of either 193 (T1
mode) or 256 (E1 mode) or 512 (4.096MHz mode) or 1024 (8.192MHz mode) RC clocks. It is acceptable to pulse
the RS signal once to establish byte boundaries and allow the DS31256 to track the byte/frame boundaries by
counting RC clocks. If the incoming data does not require alignment to byte/frame boundaries, this signal should
be wired low.
Table 3-B. RS Sampled Edge
0 RC Clock Early Mode
1/2 RC Clock Early Mode
1 RC Clock Early Mode
2 RC Clock Early Mode
Signal Name:
Signal Description:
Signal Type:
Data can be clocked out of the device either on rising edges (normal clock mode) or falling edges (inverted clock
mode) of TC. This is programmable on a per port basis. TC0 and TC1 can operate at speeds up to 52MHz. TC2–
TC15 can operate at speeds up to 10MHz. Unused signals should be wired low.
Signal Name:
Signal Description:
Signal Type:
This can be updated either on the rising edge of TC (normal clock mode) or the falling edge of TC (inverted clock
mode). Data can be forced high.
SIGNAL
RC0 to RC15
Receive Serial Clock
Input
RD0 to RD15
Receive Serial Data
Input
RS0 to RS15
Receive Serial Data Synchronization Pulse
Input
TC0 to TC15
Transmit Serial Clock
Input
TD0 to TD15
Transmit Serial Data
Output
NORMAL RC CLOCK MODE
Falling Edge
Falling Edge
Falling Edge
Rising Edge
18 of 183
INVERTED RC CLOCK MODE
Falling Edge
Rising Edge
Rising Edge
Rising Edge
(Table
3-B). The