DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 130

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.
10.1 General Description of Operation
The PCI block interfaces the DMA block to an external high-speed bus. The PCI block complies with
Revision 2.1 (June 1, 1995) of the PCI Local Bus Specification. HDLC packet data always passes to and
from the DS31256 through the PCI bus. The user has the option to configure and monitor the internal
device registers either through the PCI bus (local bus bridge mode) or through the local bus (local bus
configuration mode). When the local bus bridge mode is used, the host on the PCI bus can also bridge to
the local bus and sets/monitors the PCI configuration registers. When the local bus configuration mode is
used, the CPU on the local bus sets/monitors the PCI configuration registers.
The PCI configuration registers
apply to the PCI configuration registers:
1) All unused locations (the shaded areas of
2) Read-only locations can be written with either 1 or 0 with no effect.
3) All bits are read/write, unless otherwise noted.
Figure 10-1. PCI Configuration Memory Map
PCI BUS
0x000
0x004
0x008
0x00C
0x010
0x03C
0x100
0x104
0x108
0x10C
0x110
0x13C
Base Address for Local Bus
Max. Latency
Base Address for Device Configuration
(Figure
Device ID
Status
Device ID
Status
10-1) are described in detail in Section 10.2. The following notes
Class Code
Class Code
Header Type
Header Type
Min. Grant
Figure
130 of 183
10-1) return zeros when read.
Latency Timer
Interrupt Pin
Interrupt Pin
0x00000
Vendor ID
Command
Vendor ID
Command
Cache Line Size
0x000
Revision ID
Interrupt Line
Revision ID
Interrupt Line